Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63008 )

Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
......................................................................

soc/intel/alderlake: Use coreboot native event handler for FSP-M/S

This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.

Signed-off-by: Subrata Banik 
Change-Id: I665def977faaae45f6f834d75e8456859093ba49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 4a27cb5..bd2c0be 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <fsp/api.h>
+#include <fsp/fsp_debug_event.h>
 #include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
 #include <option.h>
@@ -509,6 +510,8 @@
 static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
+		s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler);
    /* PCH UART selection for FSP Debug */
    s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
    ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 2a02c21..2e76cd7 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -6,6 +6,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <device/device.h>
 #include <drivers/wifi/generic/wifi.h>
+#include <fsp/fsp_debug_event.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pcie_rp.h>
@@ -364,6 +365,11 @@
 {
    const struct soc_intel_alderlake_config *config;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
+
+	if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
+		arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
+						fsp_debug_event_handler);

config = config_of_soc();