Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23777
Change subject: soc/cavium: Make proper use of addressmap.h ......................................................................
soc/cavium: Make proper use of addressmap.h
Removed hardcoded addresses and use addressmap.h instead.
Change-Id: I5f0463eb202fb45ec3c2340c4389028758de688a Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/cavium/cn81xx/Kconfig M src/soc/cavium/cn81xx/Makefile.inc M src/soc/cavium/cn81xx/bootblock_custom.S M src/soc/cavium/cn81xx/include/soc/addressmap.h M src/soc/cavium/cn81xx/include/soc/memlayout.ld D src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/common/clock.c M src/soc/cavium/common/gpio.c M src/soc/cavium/common/include/soc/twsi.h M src/soc/cavium/common/twsi.c 10 files changed, 72 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23777/1
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 914bcf7..0693033 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -30,11 +30,6 @@ # select VBOOT_OPROM_MATTERS # select VBOOT_STARTS_IN_BOOTBLOCK
-# Address the BOOTROM loads the bootblock to -config BOOTROM_OFFSET - hex - default 0x100000 - config PMIC_BUS int default -1 diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index 91d71dd..c16c378 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -27,13 +27,10 @@ #bootblock-y += ../common/pwm.c bootblock-y += bootblock.c #bootblock-y += gpio.c -bootblock-y += twsi.c bootblock-y += l2c.c bootblock-y += mmu_operations.c #bootblock-y += sdram.c
-romstage-y += twsi.c - romstage-y += sdram.c romstage-y += ../common/bdk/libdram/libdram.c romstage-y += ../common/bdk/libbdk-arch/bdk-csr.c @@ -92,7 +89,6 @@ ramstage-y += ../common/cbmem.c ramstage-y += sdram.c ramstage-y += spi.c -ramstage-y += twsi.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c #ramstage-y += ../common/gpio.c #ramstage-y += gpio.c diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index fab2e43..69985b7 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -16,6 +16,7 @@ */
#include <arch/asm.h> +#include <soc/addressmap.h>
ENTRY(_start) .org 0 @@ -50,19 +51,15 @@ #error Unknown endianness #endif
- #define BDK_LMCX 0x87e088000000ULL - #define DDR_PLL_CTL0 0x258 - mov x0, (BDK_LMCX >> 32) + mov x0, (LMC0_PF_BAR0 >> 32) lsl x0, x0, 32 - mov x1, (BDK_LMCX & 0xffffffff) + mov x1, (LMC0_PF_BAR0 & 0xffffffff) orr x0, x0, x1
/* Test if DRAM PLL is running */ - ldr x1, [x0, DDR_PLL_CTL0] + ldr x1, [x0, LMC0_DDR_PLL_CTL0]
tst x1, 0x80 - #undef BDK_LMCX - #undef DDR_PLL_CTL0
b.ne cache_setup_done
@@ -81,7 +78,7 @@ node_check_done: /* Get code position */ mov x1, 0x020000 - mov x0, CONFIG_BOOTROM_OFFSET + mov x0, BOOTROM_OFFSET add x1, x0, x1
adr x0, _start @@ -114,7 +111,7 @@ adr x0, after_relocate /* Relative address */ adr x1, _start /* Relative address */ sub x0, x0, x1 /* This only works if _start is suppose to be zero */ - mov x1, CONFIG_BOOTROM_OFFSET + mov x1, BOOTROM_OFFSET add x0, x0, x1 br x0 /* Branch to relocated code */
@@ -148,13 +145,12 @@ * - CN83XX * - CN88XX */ - #define L2C_ASC_REGIONX 0x87E080800000 #define REGIONX_START 0x1000 #define REGIONX_END 0x1008 #define REGIONX_ATTR 0x1010 - mov x0, L2C_ASC_REGIONX >> 32 + mov x0, L2C_PF_BAR0 >> 32 lsl x0, x0, 32 - mov x1, (L2C_ASC_REGIONX & 0xffffffff) + mov x1, (L2C_PF_BAR0 & 0xffffffff) orr x0, x0, x1 str xzr, [x0, REGIONX_START] /* Start of zero */ mov x1, 0x3fffff00000 /* End of max address */ @@ -168,7 +164,6 @@ mov x1, L2C_WPAR_PP0_OFFSET str xzr, [x0, x1] ldr xzr, [x0, x1] /* Read back to make sure done */ - #undef L2C_ASC_REGIONX #undef REGIONX_START #undef REGIONX_END #undef REGIONX_ATTR @@ -233,12 +228,10 @@ * address space, some interrupt flags had been set. * Tidy up our mess now on (valid for CN81XX only). */ - #define L2C_TAD0_INT_W1C 0x87e050040000ULL mov x0, (L2C_TAD0_INT_W1C >> 32) lsl x0, x0, 32 mov x1, (L2C_TAD0_INT_W1C & 0xffffffff) orr x0, x0, x1 - #undef L2C_TAD0_INT_W1C
ldr x1, [x0] orr x1, x1, 0x1c00 /* Clear WRDISLMC, RDDISLMC, RDNXM */ diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index 01fd6ae..e235494 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -16,86 +16,100 @@ #ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ #define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__
-#define MAX_DRAM_ADDRESS 0x2000000000 /* 128GB */ +#define MAX_DRAM_ADDRESS 0x2000000000ULL /* 128GB */
/* Physical addressed with bit 47 set indicate I/O memory space. */
+/* ARM code entry vector */ +#define BOOTROM_OFFSET 0x100000 + /* L2C */ -#define L2C_PF_BAR0 0x87E080800000 -#define L2C_TAD0_PF_BAR0 (0x87E050000000 + 0x10000) -#define L2C_CBC0_PF_BAR0 0x87E058000000 -#define L2C_MCI0_PF_BAR0 0x87E05C000000 +#define L2C_PF_BAR0 0x87E080800000ULL +#define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000) +#define L2C_TAD0_INT_W1C (0x87E050000000ULL + 0x40000) +#define L2C_CBC0_PF_BAR0 0x87E058000000ULL +#define L2C_MCI0_PF_BAR0 0x87E05C000000ULL
/* LMC */ -#define LMC0_PF_BAR0 0x87E088000000 +#define LMC0_PF_BAR0 0x87E088000000ULL +#define LMC0_DDR_PLL_CTL0 0x258
/* OCLA */
/* IOB */ -#define IOBN0_PF_BAR0 0x87E0F0000000 -#define MRML_PF_BAR0 0x87E0FC000000 +#define IOBN0_PF_BAR0 0x87E0F0000000ULL +#define MRML_PF_BAR0 0x87E0FC000000ULL
/* SMMU */ -#define SMMU_PF_BAR0 0x830000000000 +#define SMMU_PF_BAR0 0x830000000000ULL
/* GTI */ -#define GTI_PF_BAR0 0x844000000000 +#define GTI_PF_BAR0 0x844000000000ULL
/* PCC */ -#define ECAM_PF_BAR2 0x848000000000 +#define ECAM_PF_BAR2 0x848000000000ULL
/* CPT */ /* SLI */
/* RST */ -#define RST_PF_BAR0 (0x87E006000000 + 0x1600) -#define FUSF_PF_BAR0 0x87E004000000 -#define MIO_FUS_PF_BAR0 0x87E003000000 -#define MIO_BOOT_PF_BAR0 0x87E000000000 +#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600) +#define FUSF_PF_BAR0 0x87E004000000ULL +#define MIO_FUS_PF_BAR0 0x87E003000000ULL +#define MIO_BOOT_PF_BAR0 0x87E000000000ULL
/* PTP */ -#define MIO_PTP_PF_BAR0 0x807000000000 +#define MIO_PTP_PF_BAR0 0x807000000000ULL
/* GIC */ /* NIC */ /* LBK */
-#define GTI_PF_BAR0 0x844000000000 +#define GTI_PF_BAR0 0x844000000000ULL
/* DAP */ /* BCH */ /* KEY */ /* RNG */
-#define GSER0_PF_BAR0 (0x87E090000000 + (0 << 24)) -#define GSER1_PF_BAR0 (0x87E090000000 + (1 << 24)) -#define GSER2_PF_BAR0 (0x87E090000000 + (2 << 24)) -#define GSER3_PF_BAR0 (0x87E090000000 + (3 << 24)) +#define GSER0_PF_BAR0 (0x87E090000000ULL + (0 << 24)) +#define GSER1_PF_BAR0 (0x87E090000000ULL + (1 << 24)) +#define GSER2_PF_BAR0 (0x87E090000000ULL + (2 << 24)) +#define GSER3_PF_BAR0 (0x87E090000000ULL + (3 << 24)) +#define GSERx_PF_BAR0(x) \ + ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \ + (0x87E090000000ULL + ((x) << 24)) : 0)
/* PEM */ /* SATA */ /* USB */
/* UAA */ -#define UAA0_PF_BAR0 (0x87E028000000 + (0 << 24)) -#define UAA1_PF_BAR0 (0x87E028000000 + (1 << 24)) -#define UAA2_PF_BAR0 (0x87E028000000 + (2 << 24)) -#define UAA3_PF_BAR0 (0x87E028000000 + (3 << 24)) +#define UAA0_PF_BAR0 (0x87E028000000ULL + (0 << 24)) +#define UAA1_PF_BAR0 (0x87E028000000ULL + (1 << 24)) +#define UAA2_PF_BAR0 (0x87E028000000ULL + (2 << 24)) +#define UAA3_PF_BAR0 (0x87E028000000ULL + (3 << 24)) +#define UAAx_PF_BAR0(x) \ + ((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \ + (0x87E028000000ULL + ((x) << 24)) : 0) +
/* TWSI */ -#define MIO_TWS0_PF_BAR0 (0x87E0D0000000 + (0 << 24)) -#define MIO_TWS1_PF_BAR0 (0x87E0D0000000 + (1 << 24)) +#define MIO_TWS0_PF_BAR0 (0x87E0D0000000ULL + (0 << 24)) +#define MIO_TWS1_PF_BAR0 (0x87E0D0000000ULL + (1 << 24)) +#define MIO_TWSx_PF_BAR0(x) \ + ((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0)
/* GPIO */ -#define GPIO_PF_BAR0 0x803000000000 +#define GPIO_PF_BAR0 0x803000000000ULL
/* SGPIO */ -#define SGP_PF_BAR0 0x803000000000 +#define SGP_PF_BAR0 0x803000000000ULL
/* SMI */
/* SPI */ -#define MPI_PF_BAR0 (0x804000000000 + 0x1000) +#define MPI_PF_BAR0 (0x804000000000ULL + 0x1000)
/* PCM */ /* PBUS */ @@ -104,6 +118,6 @@
/* VRM */ /* VRM BARs are spaced apart by 0x1000000 */ -#define VRM0_PF_BAR0 0x87E021000000 +#define VRM0_PF_BAR0 0x87E021000000ULL
#endif /* __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ */ diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 42e62e4..949702d 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -15,6 +15,7 @@ */
#include <memlayout.h> +#include <soc/addressmap.h> #include <arch/header.ld>
SECTIONS @@ -37,17 +38,17 @@ */
/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ - SRAM_START(CONFIG_BOOTROM_OFFSET) - STACK(CONFIG_BOOTROM_OFFSET, 16K) + SRAM_START(BOOTROM_OFFSET) + STACK(BOOTROM_OFFSET, 16K)
- PRERAM_CBFS_CACHE(CONFIG_BOOTROM_OFFSET + 0x4000, 8K) - TIMESTAMP(CONFIG_BOOTROM_OFFSET + 0x6000, 2K) - PRERAM_CBMEM_CONSOLE(CONFIG_BOOTROM_OFFSET + 0x8000, 8K) + PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x4000, 8K) + TIMESTAMP(BOOTROM_OFFSET + 0x6000, 2K) + PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
- BOOTBLOCK(CONFIG_BOOTROM_OFFSET + 0x20000, 64K) - TTB(CONFIG_BOOTROM_OFFSET + 0x30000, 64K) - ROMSTAGE(CONFIG_BOOTROM_OFFSET + 0x40000, 256K) - SRAM_END(CONFIG_BOOTROM_OFFSET + 0x80000) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + TTB(BOOTROM_OFFSET + 0x30000, 64K) + ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) + SRAM_END(BOOTROM_OFFSET + 0x80000)
POSTRAM_CBFS_CACHE(0x2000000, 1M) RAMSTAGE(0x3000000, 256K) diff --git a/src/soc/cavium/cn81xx/twsi.c b/src/soc/cavium/cn81xx/twsi.c deleted file mode 100644 index a87de79..0000000 --- a/src/soc/cavium/cn81xx/twsi.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright 2018-present Facebook, Inc. - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <stddef.h> -#include <assert.h> -#include <soc/twsi.h> - -static void *const twsi_bus[] = { - (void *const)0x87E0D0000000ULL, - (void *const)0x87E0D1000000ULL, -}; - -void *twsi_get_baseaddr(const size_t bus) -{ - assert (bus < ARRAY_SIZE(twsi_bus)); - if (bus >= ARRAY_SIZE(twsi_bus)) - return NULL; - return twsi_bus[bus]; -} diff --git a/src/soc/cavium/common/clock.c b/src/soc/cavium/common/clock.c index 1a5664d..14ab58a 100644 --- a/src/soc/cavium/common/clock.c +++ b/src/soc/cavium/common/clock.c @@ -7,8 +7,8 @@ */ #include <soc/clock.h> #include <arch/io.h> +#include <soc/addressmap.h>
-#define RST_BOOT ((void *const)0x87e006001600ll) #define PLL_REF_CLK 50000000 /* 50 MHz */
union cavm_rst_boot { @@ -53,7 +53,7 @@ { union cavm_rst_boot rst_boot;
- rst_boot.u = read64(RST_BOOT); + rst_boot.u = read64((void *)RST_PF_BAR0);
return rst_boot.s.pnr_mul * PLL_REF_CLK; } @@ -65,7 +65,7 @@ { union cavm_rst_boot rst_boot;
- rst_boot.u = read64(RST_BOOT); + rst_boot.u = read64((void *)RST_PF_BAR0);
return rst_boot.s.c_mul * PLL_REF_CLK; } diff --git a/src/soc/cavium/common/gpio.c b/src/soc/cavium/common/gpio.c index b7620e5..222ecdd 100644 --- a/src/soc/cavium/common/gpio.c +++ b/src/soc/cavium/common/gpio.c @@ -8,6 +8,7 @@ #include <soc/gpio.h> #include <arch/io.h> #include <endian.h> +#include <soc/addressmap.h>
union gpio_const { u64 u; @@ -47,9 +48,9 @@ };
/* Base address of GPIO BAR */ -static void *gpio_get_baseaddr(void) +static const void *gpio_get_baseaddr(void) { - return (void *)0x803000000000ULL; + return (const void *)GPIO_PF_BAR0; }
/* Number of GPIO pins. Usually 48. */ diff --git a/src/soc/cavium/common/include/soc/twsi.h b/src/soc/cavium/common/include/soc/twsi.h index a9f23ad..f5c1f45 100644 --- a/src/soc/cavium/common/include/soc/twsi.h +++ b/src/soc/cavium/common/include/soc/twsi.h @@ -9,6 +9,5 @@ #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H
int twsi_init(unsigned int bus, enum i2c_speed hz); -void *twsi_get_baseaddr(const size_t bus);
#endif diff --git a/src/soc/cavium/common/twsi.c b/src/soc/cavium/common/twsi.c index d9fd3fb..e6254ee 100644 --- a/src/soc/cavium/common/twsi.c +++ b/src/soc/cavium/common/twsi.c @@ -12,6 +12,7 @@ #include <assert.h> #include <delay.h> #include <arch/io.h> +#include <soc/addressmap.h>
#define TWSI_THP 24
@@ -644,7 +645,7 @@
int twsi_init(unsigned int bus, enum i2c_speed hz) { - void *baseaddr = twsi_get_baseaddr(bus); + void *baseaddr = (void *)MIO_TWSx_PF_BAR0(bus); if (!baseaddr) return -1;
@@ -661,7 +662,7 @@ int seg_count) { int result; - void *baseaddr = twsi_get_baseaddr(bus); + void *baseaddr = (void *)MIO_TWSx_PF_BAR0(bus); if (!baseaddr) return -1;
-
Patrick Rudolph (Code Review)