[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email )

(

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/glinda: Update pci int defs
......................................................................

soc/amd/glinda: Update pci int defs

Update IRQs according to datasheet/PPR.

source:
PPR #57254 Rev 1.59 Table 137

Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d
Signed-off-by: Maximilian Brune 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375
Reviewed-by: Marshall Dawson 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/glinda/acpi/pci_int_defs.asl
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
3 files changed, 15 insertions(+), 16 deletions(-)

Approvals:
  Marshall Dawson: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/soc/amd/glinda/acpi/pci_int_defs.asl b/src/soc/amd/glinda/acpi/pci_int_defs.asl
index dfbf5c7..61ecd44 100644
--- a/src/soc/amd/glinda/acpi/pci_int_defs.asl
+++ b/src/soc/amd/glinda/acpi/pci_int_defs.asl
@@ -22,7 +22,9 @@
    PIRG, 0x00000008,	/* Index 6: INTG */
    PIRH, 0x00000008,	/* Index 7: INTH */

-	Offset (0x62),
+	Offset (0x60),
+	PGSC, 0x00000008,	/* Index 0x60: GEventSci */
+	PGSM, 0x00000008,	/* Index 0x61: GEventSmi */
    PGPI, 0x00000008,	/* Index 0x62: GPIO */

Offset (0x70),
@@ -32,7 +34,8 @@
    PI23, 0x00000008,	/* Index 0x73: I2C3 */
    PUA0, 0x00000008,	/* Index 0x74: UART0 */
    PUA1, 0x00000008,	/* Index 0x75: UART1 */
-	PI24, 0x00000008,	/* Index 0x76: I2C4 */
+
+	Offset (0x77),
    PUA4, 0x00000008,	/* Index 0x77: UART4 */
    PUA2, 0x00000008,	/* Index 0x78: UART2 */
    PUA3, 0x00000008,	/* Index 0x79: UART3 */
@@ -49,6 +52,8 @@
    IORH, 0x00000008,	/* Index 0x87: INTH */

Offset (0xE2),
+	IGSC, 0x00000008,	/* Index 0xE0: GEventSci */
+	IGSM, 0x00000008,	/* Index 0xE1: GEventSmi */
    IGPI, 0x00000008,	/* Index 0xE2: GPIO */

Offset (0xF0),
@@ -58,7 +63,8 @@
    II23, 0x00000008,	/* Index 0xF3: I2C3 */
    IUA0, 0x00000008,	/* Index 0xF4: UART0 */
    IUA1, 0x00000008,	/* Index 0xF5: UART1 */
-	II24, 0x00000008,	/* Index 0xF6: I2C4 */
+
+	Offset (0xF7),
    IUA4, 0x00000008,	/* Index 0xF7: UART4 */
    IUA2, 0x00000008,	/* Index 0xF8: UART2 */
    IUA3, 0x00000008,	/* Index 0xF9: UART3 */
diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c
index 8c58f5b..c119738 100644
--- a/src/soc/amd/glinda/fch.c
+++ b/src/soc/amd/glinda/fch.c
@@ -48,16 +48,13 @@
    { PIRQ_SMBUS,	"SMBUS" },
    { PIRQ_ASF,	"ASF" },
    { PIRQ_PMON,	"PerMon" },
-	{ PIRQ_SD,	"SD" },
    { PIRQ_SDIO,	"SDIO" },
    { PIRQ_CIR,	"CIR" },
    { PIRQ_GPIOA,	"GPIOa" },
    { PIRQ_GPIOB,	"GPIOb" },
    { PIRQ_GPIOC,	"GPIOc" },
-	{ PIRQ_GPP0,	"GPP0" },
-	{ PIRQ_GPP1,	"GPP1" },
-	{ PIRQ_GPP2,	"GPP2" },
-	{ PIRQ_GPP3,	"GPP3" },
+	{ PIRQ_GSCI,	"GEventSci" },
+	{ PIRQ_GSMI,	"GeventSmi" },
    { PIRQ_GPIO,	"GPIO" },
    { PIRQ_I2C0,	"I2C0" },
    { PIRQ_I2C1,	"I2C1" },
diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
index ebe1d2c..3a9d9b5 100644
--- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
+++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
@@ -32,20 +32,16 @@
 #define PIRQ_ASF	0x12	/* ASF */
 /* 0x13-0x15 reserved */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_SD		0x17	/* SD */
-/* 0x18-0x19 reserved */
+/* 0x17-0x19 reserved */
 #define PIRQ_SDIO	0x1a	/* SDIO */
 /* 0x1b-0x1f reserved */
 #define PIRQ_CIR	0x20	/* CIR, no IRQ connected */
 #define PIRQ_GPIOA	0x21	/* GPIOa from PAD_FANIN0 */
 #define PIRQ_GPIOB	0x22	/* GPIOb from PAD_FANOUT0 */
 #define PIRQ_GPIOC	0x23	/* GPIOc no IRQ connected */
-/* 0x24-0x4f reserved */
-#define PIRQ_GPP0	0x50	/* GPPInt0 */
-#define PIRQ_GPP1	0x51	/* GPPInt1 */
-#define PIRQ_GPP2	0x52	/* GPPInt2 */
-#define PIRQ_GPP3	0x53	/* GPPInt3 */
-/* 0x54-0x61 reserved */
+/* 0x24-0x5f reserved */
+#define PIRQ_GSCI	0x60	/* GEventSci Interrupt */
+#define PIRQ_GSMI	0x61	/* GEventSmi Interrupt */
 #define PIRQ_GPIO	0x62	/* GPIO Controller Interrupt */
 /* 0x63-0x6f reserved */
 #define PIRQ_I2C0	0x70	/* I2C0 */