[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism

[Lawrence Chang (Code Review)]

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Lawrence Chang, Nick Vaccaro, Simon Yang.

Hello Curtis Chen, David Ruth, David Ruth, Jamie Chen, Nick Vaccaro, Simon Yang, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84866?usp=email

to look at the new patch set (#4).

Change subject: soc/intel/jasperlake: add support for RP LTR mechanism
......................................................................

soc/intel/jasperlake: add support for RP LTR mechanism

Reserve Root Port LTR mechanism in FSP, in case some devices
need to optimize LTR.

BUG=366383364
TEST=Tested on Awasuki with RTL8852BE
use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable
bit is offset 68h[10].
00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01)
00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20
20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00
40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08
50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00
60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00
70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00
90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00
a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00
e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00
f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84

Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f
Signed-off-by: Lawrence Chang 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/84866/4