Change in ...coreboot[master]: soc/amd/stoneyridge: Finish read/write misc registers

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32646 )

Change subject: soc/amd/stoneyridge: Finish read/write misc registers
......................................................................

soc/amd/stoneyridge: Finish read/write misc registers

Add 16 and 32-bit versions of read / write_misc functions.  Find one
access of the MISC block still using read8() and write8(), and convert
it.

Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) 
Reviewed-by: Martin Roth 
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sb_util.c
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 26 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 098d24e..e5ba2af 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -503,7 +503,11 @@
 void acpi_write8(u8 reg, u8 value);
 void acpi_write16(u8 reg, u16 value);
 void acpi_write32(u8 reg, u32 value);
+u8 misc_read8(u8 reg);
+u16 misc_read16(u8 reg);
 u32 misc_read32(u8 reg);
+void misc_write8(u8 reg, u8 value);
+void misc_write16(u8 reg, u16 value);
 void misc_write32(u8 reg, u32 value);
 uint8_t smi_read8(uint8_t offset);
 uint16_t smi_read16(uint8_t offset);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 530e9cd..5aec431 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -219,11 +219,31 @@

/* misc read/write - access registers at 0xfed80e00 */

+u8 misc_read8(u8 reg)
+{
+	return read8((void *)(ACPIMMIO_MISC_BASE + reg));
+}
+
+u16 misc_read16(u8 reg)
+{
+	return read16((void *)(ACPIMMIO_MISC_BASE + reg));
+}
+
 u32 misc_read32(u8 reg)
 {
    return read32((void *)(ACPIMMIO_MISC_BASE + reg));
 }

+void misc_write8(u8 reg, u8 value)
+{
+	write8((void *)(ACPIMMIO_MISC_BASE + reg), value);
+}
+
+void misc_write16(u8 reg, u16 value)
+{
+	write16((void *)(ACPIMMIO_MISC_BASE + reg), value);
+}
+
 void misc_write32(u8 reg, u32 value)
 {
    write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 7dc27c8..b590178 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -391,14 +391,12 @@
 void sb_clk_output_48Mhz(u32 osc)
 {
    u32 ctrl;
-	u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(ACPIMMIO_MISC_BASE
-				+ MISC_CLK_CNTL1);

/*
     * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
     * or OSCOUT2 (USBCLK/25M_48M_OSC).  The frequency defaults to 48MHz.
     */
-	ctrl = read32(misc_clk_cntl_1_ptr);
+	ctrl = misc_read32(MISC_CLK_CNTL1);

switch (osc) {
    case 1:
@@ -410,7 +408,7 @@
    default:
    	return; /* do nothing if invalid */
    }
-	write32(misc_clk_cntl_1_ptr, ctrl);
+	misc_write32(MISC_CLK_CNTL1, ctrl);
 }

static uintptr_t sb_spibase(void)