Change in coreboot[master]: mb/intel/adlrvp: Update GPIO configuration as per schematics
Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
mb/intel/adlrvp: Update GPIO configuration as per schematics
Configure I2C related GPIO as per ADL-P Schematics
Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/1
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index f91b94f..9f96620 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -134,22 +134,16 @@ /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
- /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
- /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
- /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -158,34 +152,26 @@ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
/* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
/* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG@9 PS1, Line 9: Schematics schematics
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG@10 PS1, Line 10: Please mention where the incorrect values came from. Copied or is there a new revision.
Hello V Sowmya, build bot (Jenkins), Subrata Banik, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47495
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
mb/intel/adlrvp: Update GPIO configuration as per schematics
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics.
Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/2
Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG@9 PS1, Line 9: Schematics
schematics
Done
https://review.coreboot.org/c/coreboot/+/47495/1//COMMIT_MSG@10 PS1, Line 10:
Please mention where the incorrect values came from. Copied or is there a new revision.
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
Patch Set 2: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
Patch Set 4: Code-Review+2
Subrata Banik has uploaded a new patch set (#5) to the change originally created by Varshit B Pandya. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
mb/intel/adlrvp: Update GPIO configuration as per schematics
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics.
Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/5
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
Patch Set 5: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47495 )
Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics ......................................................................
mb/intel/adlrvp: Update GPIO configuration as per schematics
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics.
Signed-off-by: Varshit Pandya varshit.b.pandya@intel.com Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 12 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 4cb8c3a..9b94cec 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -138,22 +138,16 @@ /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
- /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
- /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
- /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -162,34 +156,26 @@ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),
/* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
/* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), @@ -255,10 +241,6 @@
/* USB2 OC0 pins */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* USB2 OC1 pins */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* USB2 OC2 pins */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB2 OC3 pins */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
@@ -267,8 +249,6 @@ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-
Paul Menzel (Code Review) -
Subrata Banik (Code Review)
-
V Sowmya (Code Review)
-
Varshit B Pandya (Code Review)