Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80272?usp=email )
Change subject: soc/amd: factor out memmap from root_complex ......................................................................
soc/amd: factor out memmap from root_complex
Now that the SoC-specific memory map is reported on the domain device instead of the northbridge device, factor out the read_soc_memmap_resources function from root_complex.c to new memmap.c file. For now each SoC still has its own memmap.c file, but the plan is to eventually have a common implementation that works for all AMD family 17h+ SoCs. For that I'll still need to look closer into the differences between the FSP and the openSIL integration though.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 --- M src/soc/amd/cezanne/Makefile.mk A src/soc/amd/cezanne/memmap.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/Makefile.mk A src/soc/amd/glinda/memmap.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/Makefile.mk A src/soc/amd/mendocino/memmap.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/memmap.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/Makefile.mk A src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/root_complex.c 15 files changed, 494 insertions(+), 479 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80272/1
diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 163f777..73be4aa 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -25,6 +25,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c
diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c new file mode 100644 index 0000000..6c8e932 --- /dev/null +++ b/src/soc/amd/cezanne/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 876f790..0fb086f 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -48,96 +42,6 @@ }, \ }
-/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk index 4570e07..1211c45 100644 --- a/src/soc/amd/glinda/Makefile.mk +++ b/src/soc/amd/glinda/Makefile.mk @@ -29,6 +29,7 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c
diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/glinda/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 9d83f6f..36942bf 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Glinda */
#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,96 +57,6 @@ }, \ }
-/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk index cc44358..a72116e 100644 --- a/src/soc/amd/mendocino/Makefile.mk +++ b/src/soc/amd/mendocino/Makefile.mk @@ -27,6 +27,7 @@ ramstage-y += fsp_misc_data_hob.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c ramstage-y += manifest.c diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/mendocino/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 5561240..3247eb4 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Check if this is still correct */
#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/amd_misc_data.h> @@ -91,96 +85,6 @@ }, \ }
-/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 26e9102..feb9b1a 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -31,6 +31,7 @@ ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += soc_util.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c new file mode 100644 index 0000000..432d850 --- /dev/null +++ b/src/soc/amd/phoenix/memmap.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + if (CONFIG(PLATFORM_USES_FSP2_0)) + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 4a657f8..4ce5f2a 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Phoenix */
#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,97 +57,6 @@ }, \ }
-/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - if (CONFIG(PLATFORM_USES_FSP2_0)) - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index 94d7f7bb..3fcd47f 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -26,6 +26,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += pcie_gpp.c ramstage-y += root_complex.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c new file mode 100644 index 0000000..7ec7adf --- /dev/null +++ b/src/soc/amd/picasso/memmap.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/memmap.h> +#include <amdblocks/iomap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 1e702ab..d4e8401 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -1,18 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> -#include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <assert.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <stdint.h> @@ -48,93 +41,6 @@ }, \ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -}
static void root_complex_init(struct device *dev) {
-
Felix Held (Code Review)