[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email )

Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
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Patch Set 5:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81098/comment/6dfdfb55_1f0e87af :
PS5, Line 14: Additionally, the assumption of socket0/stack0 is a PCIe stack is not
            : always true for future generation SoCs and hence this assumption is
            : removed.
> sidenote: This is still assumed in iio_pci_domain_read_resources.

I see, domain0 as PCIe still stands though the whole stack might not be (e.g. a mixed stack). I will remove this paragraph to avoid confusion.

Patchset:

PS5:
> Looks good to me, but I do have question on how to handle the statically created devicetree structur […]

Yeah, this issue is handled. All domain creation func is changed from alloc_dev to alloc_find_dev to make sure that, for domain0/socket0 which is already created statically, the static one will be used. And I also checked the logs to make sure there is no duplicated domain0 processing.