Change in coreboot[master]: soc/intel/skylake: Add Kconfig option to select UART index

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20996

Change subject: soc/intel/skylake: Add Kconfig option to select UART index
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soc/intel/skylake: Add Kconfig option to select UART index

Skylake/Kabylake SOC has two possible ways to make serial
console functional. 1. Using 0x3F8 as Legacy UART 2. PCI
based LPSS UART2

PCI based LPSS UART2 is default enable for Chrome Design.

Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/20996/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f0402a9..2fba1d4 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -200,6 +200,13 @@
    select DRIVERS_UART_8250MEM_32
    select NO_UART_ON_SUPERIO

+config UART_FOR_CONSOLE
+	int
+	default 2
+	help
+	    Index for UART port to use for console:
+	    0 = Legacy UART, 2 = LPSS UART2
+
 config SKYLAKE_SOC_PCH_H
    bool
    default n