Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59674 )

Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
......................................................................

soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs

Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the
LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04,
Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and
Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code.

Signed-off-by: Felix Held 
Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59674/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 09eafb8..7c798d6 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -10,6 +10,8 @@
 #define   LEGACY_DMA_EN			BIT(2)
 #define   VW_ROM_SHARING_EN		BIT(3)
 #define   EXT_ROM_SHARING_EN		BIT(4)
+#define   SPI_ROM_BIOS_SEMAPHORE	BIT(5)
+#define   SPI_ROM_EC_SEMAPHORE		BIT(6)

#define LPC_IO_PORT_DECODE_ENABLE	0x44
 #define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)