[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD...

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86483?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD more preparation time
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mb/google/nissa/var/rull: Adjust SSD power sequencing to give the SSD more preparation time

Improve SSD reset time by enabling earlier sequencing, save 230ms

BUG=b:397098950
TEST=build and boot normal using NVMe

Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567
Signed-off-by: Rui Zhou 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86483
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/variants/rull/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, approved
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c
index 81bd280..24096d7 100644
--- a/src/mainboard/google/brya/variants/rull/gpio.c
+++ b/src/mainboard/google/brya/variants/rull/gpio.c
@@ -141,6 +141,8 @@
 };

static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 };

const struct pad_config *variant_gpio_override_table(size_t *num)