Change in coreboot[master]: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63547 )

Change subject: soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig
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soc/intel/elkhartlake/systemagent: Disable RAPL based on Kconfig

This patch provides the possibility for EHL based boards to disable
RAPL settings via SOC_INTEL_DISABLE_POWER_LIMITS config switch.

On Elkhart Lake the way via setting relevant MSR bits does not work.
Therefore the way via MCHBAR is choosen.

Test:
Check MCHBAR mapped registers (MCH_PKG_POWER_LIMIT) on mc_ehl1.

Change-Id: I5be6632b15ab8e14a21b5cd35152f82fec919d9f
Signed-off-by: Uwe Poeche 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63547
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/soc/intel/elkhartlake/include/soc/systemagent.h
M src/soc/intel/elkhartlake/systemagent.c
2 files changed, 15 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/include/soc/systemagent.h b/src/soc/intel/elkhartlake/include/soc/systemagent.h
index 0abfbfc..c254d64 100644
--- a/src/soc/intel/elkhartlake/include/soc/systemagent.h
+++ b/src/soc/intel/elkhartlake/include/soc/systemagent.h
@@ -21,7 +21,9 @@
 #define VTBAR_MASK		0x7ffffff000ull

#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define PKG_PWR_LIM_1_EN	(1 << 15)
 #define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define PKG_PWR_LIM_2_EN	(1 << 15)
 #define MCH_DDR_POWER_LIMIT_LO	0x58e0
 #define MCH_DDR_POWER_LIMIT_HI	0x58e4

diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c
index 02ede59..85623e8 100644
--- a/src/soc/intel/elkhartlake/systemagent.c
+++ b/src/soc/intel/elkhartlake/systemagent.c
@@ -48,6 +48,7 @@
 {
    struct soc_power_limits_config *soc_config;
    config_t *config;
+	uint32_t value;

/* Enable Power Aware Interrupt Routing */
    enable_power_aware_intr();
@@ -56,7 +57,16 @@
    enable_bios_reset_cpl();

mdelay(1);
-	config = config_of_soc();
-	soc_config = &config->power_limits_config;
-	set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+	if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
+		printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
+		/* clear bits 47, 15 in PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU */
+		value = MCHBAR32(MCH_PKG_POWER_LIMIT_LO);
+		MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_PWR_LIM_1_EN);
+		value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI);
+		MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_PWR_LIM_2_EN);
+	} else {
+		config = config_of_soc();
+		soc_config = &config->power_limits_config;
+		set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+	}
 }