[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size

[Arthur Heymans (Code Review)]

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Paul Menzel, Jon Murphy, Fred Reitberger, Karthik Ramasubramanian.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 )

Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69827/comment/ccd58bd4_0ee55ae3 
PS1, Line 11: This reduction along with the available free space in PSP shared buffer
            : (32 KiB)
> We cannot jump bump the PSP Shared buffer size in coreboot. That requires a matching change in PSP to increase the buffer from 32 KiB to 64 KiB. Probably whichever SRAM supporting that buffer should have the available space.
>
> This change tries to avoid that coupling.

Is there a reason the transfer buffer needs to be a multiple of 2? I only see that value used in 2 separate linker scripts, which should also warn you if things overflow.