Change in coreboot[master]: cpu/intel/common/fsb.c: Add Broadwell CPUID models

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49939 )

Change subject: cpu/intel/common/fsb.c: Add Broadwell CPUID models
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cpu/intel/common/fsb.c: Add Broadwell CPUID models

Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.

Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.

Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons 
---
M src/cpu/intel/common/fsb.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/49939/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 3d46bbc..68abe1c 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -44,8 +44,10 @@
    	case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
    	case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
    	case 0x3c: /* Haswell BCLK fixed at 100MHz */
+		case 0x3d: /* Broadwell-ULT BCLK fixed at 100MHz */
    	case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
    	case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */
+		case 0x47: /* Broadwell BCLK fixed at 100MHz */
    		*fsb = 100;
    		*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
    		break;