[XS] Change in coreboot[main]: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86393?usp=email )

Change subject: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel
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soc/intel/pantherlake: Skip exposing CPUJTAG at kernel

This patch avoids exposing CPUJTAG GPIO PADs as these are not internal
to SoC debugging purpose and shouldn't allow kernel level configuration.

TEST=Able to build and boot google/fatat.

Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik 
---
M src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/86393/1

diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 0937d1e..82ab6e8 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -397,7 +397,7 @@

#define NUM_GRP_VGPIO3_PADS	(GPP_VGPIO3_THC3 - GPP_VGPIO3_USB0 + 1)

-#define COM3_GRP_PAD_START	GPP_EPD_ON
+#define COM3_GRP_PAD_START	GPP_H00
 #define COM3_GRP_PAD_END	GPP_VGPIO3_THC3
 #define NUM_COM3_GRP_PADS	(GPP_VGPIO3_THC3 - GPP_EPD_ON + 1)
 #define NUM_COM3_GPP_PADS	(NUM_GPP_H_PADS + NUM_GPP_A_PADS)