Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36202 )
Change subject: [TEST]mb/asrock/g41c-gs: Move CIR init after dmi init ......................................................................
[TEST]mb/asrock/g41c-gs: Move CIR init after dmi init
Change-Id: I8a700b58c48d1f35364a2352b75d2f0cbde226cd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36202/1
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index bb7a342..090bb79 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -63,8 +63,6 @@ /* Enable IOAPIC */ RCBA8(OIC) = 0x03; RCBA8(OIC); - - ich7_setup_cir(); }
static void ich7_enable_lpc(void) @@ -103,6 +101,8 @@
x4x_late_init(s3_resume);
+ ich7_setup_cir(); + printk(BIOS_DEBUG, "x4x late init complete\n");
}
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36202
to look at the new patch set (#2).
Change subject: [TEST]mb/asrock/g41c-gs: Enable static PCIe clock gating ......................................................................
[TEST]mb/asrock/g41c-gs: Enable static PCIe clock gating
Change-Id: I8a700b58c48d1f35364a2352b75d2f0cbde226cd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36202/2
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36202
to look at the new patch set (#3).
Change subject: [TEST]mb/asrock/g41c-gs: Set VC settings before doing CIR ......................................................................
[TEST]mb/asrock/g41c-gs: Set VC settings before doing CIR
Change-Id: I8a700b58c48d1f35364a2352b75d2f0cbde226cd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/i82801gx/early_cir.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36202/3
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36202 )
Change subject: [TEST]mb/asrock/g41c-gs: Set VC settings before doing CIR ......................................................................
Abandoned
Not working
-
Arthur Heymans (Code Review)