Change in coreboot[master]: mb/starlabs/labtop: Enable I2C4

[Sean Rhodes (Code Review)]

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60264 )

Change subject: mb/starlabs/labtop: Enable I2C4
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mb/starlabs/labtop: Enable I2C4

Enable I2C4 to allow for proper enumeration but avoid FSP configuring it.

Signed-off-by: Sean Rhodes 
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
---
M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/60264/1

diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index a3fc715..ed32afc 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -28,6 +28,7 @@
    # Serial I/O
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C4]		= PchSerialIoSkipInit,
    }"

register "SerialIoUartMode" = "{
@@ -165,7 +166,7 @@
    		register "SataPortsEnable[1]"		= "1"
    		register "SataPortsDevSlp[1]"		= "1"
    	end
-		device pci 19.0 off end						# I2C4
+		device pci 19.0 on  end						# I2C4
    	device pci 19.1 off end						# I2C5
    	device pci 19.2 on  end						# UART #2
    	device pci 1c.0 off end						# PCI Express Port 1