Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41935 )
Change subject: southbridge/intel/wildcatpoint: Add ACPI ......................................................................
southbridge/intel/wildcatpoint: Add ACPI
Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/1
diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 0fa2d17..315b558 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -10,13 +10,13 @@ 0x20110725 // OEM revision ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl>
// Thermal handler #include "acpi/thermal.asl"
// global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -25,7 +25,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index ad5ca61..396f105 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ #include <variant/acpi/thermal.asl>
// global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } }
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 6453d7a..119ab89 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl"
// global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } }
diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 68e97c3..e0a07a9 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -10,10 +10,10 @@ 0x20160115 /* OEM revision */ ) { - #include <soc/intel/broadwell/acpi/platform.asl> + #include <southbridge/intel/wildcatpoint/acpi/platform.asl>
/* Global NVS and variables */ - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <southbridge/intel/wildcatpoint/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -22,7 +22,7 @@ Device (PCI0) { #include <northbridge/intel/broadwell/acpi/broadwell.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <southbridge/intel/wildcatpoint/acpi/pch.asl> } }
diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/southbridge/intel/wildcatpoint/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/southbridge/intel/wildcatpoint/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/southbridge/intel/wildcatpoint/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/southbridge/intel/wildcatpoint/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/southbridge/intel/wildcatpoint/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/southbridge/intel/wildcatpoint/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/southbridge/intel/wildcatpoint/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/southbridge/intel/wildcatpoint/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/southbridge/intel/wildcatpoint/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/southbridge/intel/wildcatpoint/acpi/platform.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/platform.asl rename to src/southbridge/intel/wildcatpoint/acpi/platform.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/southbridge/intel/wildcatpoint/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/southbridge/intel/wildcatpoint/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/southbridge/intel/wildcatpoint/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/southbridge/intel/wildcatpoint/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/southbridge/intel/wildcatpoint/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/southbridge/intel/wildcatpoint/acpi/xhci.asl
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41935
to look at the new patch set (#9).
Change subject: southbridge/intel/wildcatpoint: Add ACPI ......................................................................
southbridge/intel/wildcatpoint: Add ACPI
Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/9
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41935
to look at the new patch set (#12).
Change subject: southbridge/intel/wildcatpoint: Add ACPI ......................................................................
southbridge/intel/wildcatpoint: Add ACPI
Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/12
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41935
to look at the new patch set (#16).
Change subject: southbridge/intel/wildcatpoint: Add ACPI ......................................................................
southbridge/intel/wildcatpoint: Add ACPI
Move ACPI ASL files from the soc namespace to the southbridge scope. We also need to update the mainboard-scope dsdt.asl inclusion paths.
With BUILD_TIMELESS=1 but without adding the .config file into the resulting coreboot image, google/auron (Buddy) remains identical.
Change-Id: I28e4d437728815a4038d7e1610e12a983c578742 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/southbridge/intel/wildcatpoint/acpi/adsp.asl R src/southbridge/intel/wildcatpoint/acpi/device_nvs.asl R src/southbridge/intel/wildcatpoint/acpi/ehci.asl R src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl R src/southbridge/intel/wildcatpoint/acpi/gpio.asl R src/southbridge/intel/wildcatpoint/acpi/hda.asl R src/southbridge/intel/wildcatpoint/acpi/irqlinks.asl R src/southbridge/intel/wildcatpoint/acpi/lpc.asl R src/southbridge/intel/wildcatpoint/acpi/pch.asl R src/southbridge/intel/wildcatpoint/acpi/pcie.asl R src/southbridge/intel/wildcatpoint/acpi/pcie_port.asl R src/southbridge/intel/wildcatpoint/acpi/platform.asl R src/southbridge/intel/wildcatpoint/acpi/sata.asl R src/southbridge/intel/wildcatpoint/acpi/serialio.asl R src/southbridge/intel/wildcatpoint/acpi/smbus.asl R src/southbridge/intel/wildcatpoint/acpi/xhci.asl 20 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41935/16
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41935 )
Change subject: southbridge/intel/wildcatpoint: Add ACPI ......................................................................
Abandoned