Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39531 )
Change subject: soc/intel/tgierlake: Enable ISH ......................................................................
soc/intel/tgierlake: Enable ISH
Configure ISH based on devicetree Add ISH ACPI object name for SSDT
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I07d41558eaf1f6e047e402dbbafc62d0ddfec8c0 --- M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39531/1
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 6f6e153..dc36da3 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -71,6 +71,7 @@
switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 072c99e..208dd6f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -77,6 +77,13 @@ else m_cfg->InternalGfx = 0x1;
+ /* ISH */ + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + if (!dev || !dev->enabled) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = 1; + /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig;
Wonkyu Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39531 )
Change subject: soc/intel/tgierlake: Enable ISH ......................................................................
Abandoned
Merged the change to https://review.coreboot.org/c/coreboot/+/39480