Change in coreboot[master]: sb/intel/lynxpoint: Drop stale code paths

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42618 )

Change subject: sb/intel/lynxpoint: Drop stale code paths
......................................................................

sb/intel/lynxpoint: Drop stale code paths

These appear to be leftovers from old SMM relocation code.

Change-Id: I689bee55943b29990f54cb798b999940eae180bc
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42618
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/smi.c
1 file changed, 0 insertions(+), 32 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 102ed24..48b76e2 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -58,38 +58,6 @@
    smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }

-static void  __unused southbridge_trigger_smi(void)
-{
-	/**
-	 * There are several methods of raising a controlled SMI# via
-	 * software, among them:
-	 *  - Writes to io 0xb2 (APMC)
-	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
-	 *
-	 * Using the local APIC is a bit more tricky. According to
-	 * AMD Family 11 Processor BKDG no destination shorthand must be
-	 * used.
-	 * The whole SMM initialization is quite a bit hardware specific, so
-	 * I'm not too worried about the better of the methods at the moment
-	 */
-
-	/* raise an SMI interrupt */
-	printk(BIOS_SPEW, "  ... raise SMI#\n");
-	apm_control(APM_CNT_NOOP_SMI);
-}
-
-static void __unused southbridge_clear_smi_status(void)
-{
-	/* Clear SMI status */
-	clear_smi_status();
-
-	/* Clear PM1 status */
-	clear_pm1_status();
-
-	/* Set EOS bit so other SMIs can occur. */
-	enable_smi(EOS);
-}
-
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
    /*