Attention is currently required from: Jayvik Desai, Pranava Y N, Subrata Banik, Weimin Wu.
Tongtong Pan has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/85965?usp=email )
Change subject: mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C ......................................................................
Patch Set 2:
(5 comments)
File src/mainboard/google/fatcat/variants/felino/gpio.c:
https://review.coreboot.org/c/coreboot/+/85965/comment/b6c289fa_acd110c7?usp... : PS1, Line 281: PAD_CFG_GPI_APIC
locking make sense for ramstage but I won't lock a PAD with interrupt configuration
Done
https://review.coreboot.org/c/coreboot/+/85965/comment/653c3ff2_8fc1ee5e?usp... : PS1, Line 407: PAD_CFG_GPI_APIC_LOCK
please don't use lock macro for early GPIO configuration
Done
https://review.coreboot.org/c/coreboot/+/85965/comment/d2df5fe0_2de33919?usp... : PS1, Line 422: PAD_CFG_GPI_APIC_LOCK
same as above
Done
https://review.coreboot.org/c/coreboot/+/85965/comment/5f404074_e3e084bb?usp... : PS1, Line 415: PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), : : /* GPP_H21: PCH_I2C_GSC_SDA */ : PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), : /* GPP_H22: PCH_I2C_GSC_SCL */ : PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), : /* GPP_F15: SPI_TPM_INT_N */ : PAD_CFG_GPI_APIC_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
I don't think it's necessary to add these in romstage.
Done
File src/mainboard/google/fatcat/variants/felino/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85965/comment/29b43427_88a690ab?usp... : PS1, Line 50: register "serial_io_i2c_mode" = "{ : [PchSerialIoIndexI2C0] = PchSerialIoPci, : [PchSerialIoIndexI2C1] = PchSerialIoPci, : [PchSerialIoIndexI2C4] = PchSerialIoPci, : }"
looking at the below description I2C0 seems unused ? is this required to be enabled for making i2c1 […]
Yes,i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.