[L] Change in coreboot[main]: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile - coreboot-gerrit

5 Aug 2024


      Attention is currently required from: Ashish Kumar Mishra, Krishna P Bhat D.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 9:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/f61a6702_b44320fc?usp... :
PS9, Line 34: #pragma pack (push, 1)
...
Hi Ashish, this syntax is to Save current state and then set packing alignment to 1 byte. […]
Acknowledged
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Gerrit-Change-Number: 83732
Gerrit-PatchSet: 9
Gerrit-Owner: Saurabh Mishra mishra.saurabh@intel.com
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