Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`

[Angel Pons (Code Review)]

Attention is currently required from: Alexander Couzens, Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52072 )

Change subject: nb/intel/sandybridge: Drop `pci_mmio_size`
......................................................................

nb/intel/sandybridge: Drop `pci_mmio_size`

There's no good reason to use values smaller than 2 GiB here.

Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons 
---
M src/mainboard/google/stout/devicetree.cb
M src/mainboard/lenovo/x131e/devicetree.cb
M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
M src/mainboard/lenovo/x230/devicetree.cb
M src/mainboard/samsung/lumpy/devicetree.cb
M src/mainboard/samsung/stumpy/devicetree.cb
M src/northbridge/intel/sandybridge/chip.h
M src/northbridge/intel/sandybridge/raminit_common.c
8 files changed, 3 insertions(+), 36 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52072/1

diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 5461b15..73dce98 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -33,8 +33,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0 on
    	subsystemid 0x1ae0 0xc000 inherit
    	device pci 00.0 on end # host bridge
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index 18ed380..2627fae 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -26,8 +26,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0x0 on
    	subsystemid 0x17aa 0x21fe inherit

diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index b4d3800..5f1ea6b 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -24,8 +24,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0 on
    	subsystemid 0x17aa 0x21f9 inherit

diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index de91bba..e0557ca 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -27,8 +27,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0 on
    	subsystemid 0x17aa 0x21fa inherit

diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 0f3ee5c..6cda62b 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -31,8 +31,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0 on
    	ioapic_irq 4 INTA 0x10
    	ioapic_irq 4 INTB 0x11
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 20c994e..6f49cfe 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -23,8 +23,6 @@
    	end
    end

-	register "pci_mmio_size" = "1024"
-
    device domain 0 on
    	subsystemid 0x1ae0 0xc000 inherit
    	device pci 00.0 on end # host bridge
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
index 824af3e..99d9763 100644
--- a/src/northbridge/intel/sandybridge/chip.h
+++ b/src/northbridge/intel/sandybridge/chip.h
@@ -43,11 +43,6 @@

struct i915_gpu_controller_info gfx;

-	/*
-	 * Maximum PCI MMIO size in MiB.
-	 */
-	u16 pci_mmio_size;
-
    /* Data for RAM init */

/* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index d6a8aa5..7637f1f 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -338,24 +338,6 @@
    }
 }

-#define DEFAULT_PCI_MMIO_SIZE 2048
-
-static unsigned int get_mmio_size(void)
-{
-	const struct device *dev;
-	const struct northbridge_intel_sandybridge_config *cfg = NULL;
-
-	dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
-	if (dev)
-		cfg = dev->chip_info;
-
-	/* If this is zero, it just means devicetree.cb didn't set it */
-	if (!cfg || cfg->pci_mmio_size == 0)
-		return DEFAULT_PCI_MMIO_SIZE;
-	else
-		return cfg->pci_mmio_size;
-}
-
 /*
  * Returns the ECC mode the NB is running at. It takes precedence over ECC capability.
  * The ME/PCU/.. has the ability to change this.
@@ -382,6 +364,8 @@
    return !(reg32 & (1 << 25));
 }

+#define DEFAULT_PCI_MMIO_SIZE 2048
+
 void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
 {
    u32 reg, val, reclaim, tom, gfxstolen, gttsize;
@@ -389,7 +373,7 @@
    size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta;
    uint16_t ggc;

-	mmiosize = get_mmio_size();
+	mmiosize = DEFAULT_PCI_MMIO_SIZE;

ggc = pci_read_config16(HOST_BRIDGE, GGC);
    if (!(ggc & 2)) {