[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support

[Reka Norman (Code Review)]

Attention is currently required from: ChiaLing, Paul Menzel, Reka Norman, Ryan Lin, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Zhuohao Lee.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75406?usp=email )

Change subject: soc/intel/common: Add PsysPl1 support
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Patch Set 3:

(2 comments)

File src/soc/intel/common/block/power_limit/power_limit.c:

https://review.coreboot.org/c/coreboot/+/75406/comment/332d8c1f_efd14354 :
PS1, Line 160: tdp_psyspl1
> We can use psyspl1 to make performance more efficient.  […]

A couple more questions:
1. I thought it always uses the most restrictive limits, so it would take the minimum of PL1 and PsysPl1. So in your example if PsysPL1 is 31W, it would still limit the CPU power to PL1. Is that not right? Or does it ignore PL1 if PSYS is enabled (and in that case why do we still set PL1?)
2. Should PsysPl1 be set to the total system thermal capacity? If so, that will be much lower than 31W on dibbi since it's fanless, e.g. maybe 6W?

https://review.coreboot.org/c/coreboot/+/75406/comment/76580c6d_51081fe1 :
PS1, Line 169: 		wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
> I think line 129 to 150 already set pl1.

Line 129 to 150 is setting MSR_PKG_POWER_LIMIT. I was talking about bits 23:17 in MSR_PLATFORM_POWER_LIMIT (PsysPL1 time window, not PL1 time window).