Change in coreboot[master]: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60402 )

Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
......................................................................

drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional

The FSP API is used to notify the FSP about different phases in the
boot process. The current FSP specification supports three notify
phases:
 - Post PCI enumeration
 - Ready to Boot
 - End of Firmware

This patch attempts to make calling into the FSP Notify Phase APIs
optional by using native coreboot implementations to perform the
required lock down and chipset register configuration prior boot to
payload.

BUG=b:211954778
TEST=Able to build brya without any compilation issue and coreboot
log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled.

coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.

Signed-off-by: Subrata Banik 
Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60402
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Lean Sheng Tan 
Reviewed-by: Werner Zeh 
Reviewed-by: EricR Lai 
Reviewed-by: Paul Menzel 
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/notify.c
2 files changed, 46 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Werner Zeh: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Lean Sheng Tan: Looks good to me, approved
  EricR Lai: Looks good to me, approved

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 716e809..2992b4f 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -310,4 +310,41 @@
      SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and
      execute FspMultiPhaseSiInit() API.

+config SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM
+	bool
+	help
+	  The FSP API is used to notify the FSP about different phases in the boot process.
+	  The current FSP specification supports three notify phases:
+	  - Post PCI enumeration
+	  - Ready to Boot
+	  - End of Firmware
+	  Select this on a platform where you want to skip calling FSP Notify
+	  `Post PCI enumeration` API. Instead use coreboot native implementations
+	  to perform the required lock down and chipset register configuration prior
+	  boot to payload.
+
+config SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT
+	bool
+	help
+	  The FSP API is used to notify the FSP about different phases in the boot process.
+	  The current FSP specification supports three notify phases:
+	  - Post PCI enumeration
+	  - Ready to Boot
+	  - End of Firmware
+	  Select this on a platform where you want to skip calling FSP Notify `Ready to Boot`
+	  API. Instead use coreboot native implementations to perform the required lock down
+	  and chipset register configuration prior boot to payload.
+
+config SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
+	bool
+	help
+	  The FSP API is used to notify the FSP about different phases in the boot process.
+	  The current FSP specification supports three notify phases:
+	  - Post PCI enumeration
+	  - Ready to Boot
+	  - End of Firmware
+	  Select this on a platform where you want to skip calling FSP Notify `End of Firmware`
+	  API. Instead use coreboot native implementations to perform the required lock down
+	  and chipset register configuration prior boot to payload.
+
 endif
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index cdace31..36b538f 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -10,6 +10,7 @@

struct fsp_notify_phase_data {
    enum fsp_notify_phase notify_phase;
+	bool skip;
    uint8_t post_code_before;
    uint8_t post_code_after;
    enum timestamp_id timestamp_before;
@@ -19,6 +20,7 @@
 static const struct fsp_notify_phase_data notify_data[] = {
    {
    	.notify_phase     = AFTER_PCI_ENUM,
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM),
    	.post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE,
    	.post_code_after  = POST_FSP_NOTIFY_AFTER_ENUMERATE,
    	.timestamp_before = TS_FSP_BEFORE_ENUMERATE,
@@ -26,6 +28,7 @@
    },
    {
    	.notify_phase     = READY_TO_BOOT,
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT),
    	.post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE,
    	.post_code_after  = POST_FSP_NOTIFY_AFTER_FINALIZE,
    	.timestamp_before = TS_FSP_BEFORE_FINALIZE,
@@ -33,6 +36,7 @@
    },
    {
    	.notify_phase     = END_OF_FIRMWARE,
+		.skip             = CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE),
    	.post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE,
    	.post_code_after  = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE,
    	.timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE,
@@ -56,6 +60,11 @@
    fsp_notify_fn fspnotify;
    uint32_t ret;

+	if (data->skip) {
+		printk(BIOS_INFO, "coreboot skipped calling FSP notify phase: %08x.\n", phase);
+		return;
+	}
+
    if (!fsps_hdr.notify_phase_entry_offset)
    	die("Notify_phase_entry_offset is zero!\n");