Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25426
Change subject: soc/intel/denverton: Enable common block PMC ......................................................................
soc/intel/denverton: Enable common block PMC
Mainly updating headers to build.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert jviarddegalbert@online.net --- M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/pmutil.c 7 files changed, 28 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25426/1
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index cf87d05..6492248 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -454,6 +454,7 @@ return ps->prev_sleep_state; }
+#ifdef ETR /* * If possible, lock 0xcf9. Once the register is locked, it can't be changed. * This lock is reset on cold boot, hard reset, soft reset and Sx. @@ -486,6 +487,7 @@ reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST; write32((void *)etr, reg); } +#endif
int vboot_platform_is_resuming(void) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 35296d5..303b1e5 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -46,6 +46,8 @@ select SMP select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_INTEL_HARDWARE_SLEEP_VALUES # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 7386db3..433d611 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -129,7 +129,7 @@ fadt->pm1b_cnt_blk = 0x0; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe0_blk = pmbase + GPE0_STS(0); fadt->gpe1_blk = 0;
/* Control Registers - Length */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 29b231f..a7548d4 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -29,6 +29,7 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 #define DEFAULT_ACPI_BASE DEFAULT_PMBASE +#define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400
/* Southbridge internal device MEM BARs (Set to match FSP settings) */ diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 2dc8781..5978b3a 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -20,10 +20,10 @@
#include <arch/io.h> #include <soc/pmc.h> +#include <arch/acpi.h>
-#define SLEEP_STATE_S0 0 -#define SLEEP_STATE_S3 3 -#define SLEEP_STATE_S5 5 +/* TODO: Check that */ +#define GPE_MAX 127
struct chipset_power_state { uint16_t pm1_sts; @@ -31,8 +31,8 @@ uint32_t pm1_cnt; uint16_t tco1_sts; uint16_t tco2_sts; - uint32_t gpe0_sts[4]; - uint32_t gpe0_en[4]; + uint32_t gpe0_sts[GPE0_REG_MAX]; + uint32_t gpe0_en[GPE0_REG_MAX]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index edb5c55..4db3981 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -120,7 +120,10 @@ #define GPE_CTRL 0x40 #define SWGPE_CTRL (1 << 17) #define PM2_CNT 0x50 -#define GPE0_STS 0x80 +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x80 + (x * 4)) +#define GPE_STD 0 #define GPIO31_STS (1 << 31) #define GPIO30_STS (1 << 30) #define GPIO29_STS (1 << 29) @@ -166,7 +169,7 @@ #define IE_SCI_STS (1 << 3) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x90 +#define GPE0_EN(x) (0x90 + (x * 4)) #define GPIO31_EN (1 << 31) #define GPIO30_EN (1 << 30) #define GPIO29_EN (1 << 29) @@ -236,6 +239,12 @@ #define TCO2_CNT 0x0a #define TCO_TMR 0x12
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x10 +#define GPIO_GPE_CFG 0x120 +#define GPE0_DWX_MASK 0x7 +#define GPE0_DW_SHIFT(x) (4 + 4*(x)) + /* I/O ports */ #define RST_CNT 0xcf9 #define FULL_RST (1 << 3) diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index 542997c..6eb7db8 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -189,17 +189,17 @@ void enable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); }
void disable_gpe(uint32_t mask) { uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN)); + uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN)); + outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); }
void disable_all_gpe(void) { disable_gpe(~0); } @@ -207,8 +207,8 @@ static uint32_t reset_gpe_status(void) { uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS)); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS)); + uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); + outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); return gpe_sts; }
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Julien Viard de Galbert (Code Review)