[S] Change in coreboot[main]: cpu/x86/mtrr: Exclude ranges above 4G if temporary MTRRs exhausted

[Matt DeVillier (Code Review)]

Attention is currently required from: Jérémy Compostella, Shuo Liu.

Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86941?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: cpu/x86/mtrr: Exclude ranges above 4G if temporary MTRRs exhausted
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cpu/x86/mtrr: Exclude ranges above 4G if temporary MTRRs exhausted

mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
o which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map these
temporary regions as well as any RAM above 4GiB.

As a workaround, modify calc_var_mtrrs() to return the number of MTRRs
needed in addition to the default type, and if that number exceeds the
maximum available, retry with `above4gb` set to 0.

TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.

Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier 
---
M src/cpu/x86/mtrr/mtrr.c
1 file changed, 22 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86941/3