Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS regsion size.
BUG:b:140665483 TEST='compile successfully'
Signed-off-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35304/1
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 78b12bd..8bab919 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,26 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x402000 { + SI_ALL@0x0 0x438000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_ME@0x101000 0x2fd000 - SI_PDR(PRESERVE)@0x3fe000 0x4000 + SI_ME@0x101000 0x333000 + SI_PDR(PRESERVE)@0x434000 0x4000 } - SI_BIOS@0x402000 0x1bfe000 { - RW_DIAG@0x0 0x12ce000 { - RW_LEGACY(CBFS)@0x0 0x12be000 - DIAG_NVRAM@0x12be000 0x10000 + SI_BIOS@0x438000 0x1bc8000 { + RW_DIAG@0x0 0x1298000 { + RW_LEGACY(CBFS)@0x0 0x1288000 + DIAG_NVRAM@0x1288000 0x10000 } - RW_SECTION_A@0x12ce000 0x280000 { + RW_SECTION_A@0x1298000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x154e000 0x280000 { + RW_SECTION_B@0x1518000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17ce000 0x30000 { + RW_MISC@0x1798000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -33,7 +33,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x17fe000 0x400000 { + WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 {
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 1: Code-Review+1
LGTM
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35304/1//COMMIT_MSG@9 PS1, Line 9: This will increase ME region size and reduce the BIOS regsion size. region
Hello EricR Lai, Bernardo Perez Priego, Mathew King, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35304
to look at the new patch set (#2).
Change subject: mb/google/drallion: Update memory map ......................................................................
mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS region size.
BUG:b:140665483 TEST='compile successfully'
Signed-off-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35304/2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG@11 PS2, Line 11: BUG:b:140665483 BUG=
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG@8 PS2, Line 8: : This will increase ME region size and reduce the BIOS region size. : : BUG:b:140665483 : Remove extra tabs.
EricR Lai has uploaded a new patch set (#3) to the change originally created by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483 TEST='compile successfully'
Signed-off-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35304/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG@11 PS2, Line 11: BUG:b:140665483
BUG=
Done
https://review.coreboot.org/c/coreboot/+/35304/2//COMMIT_MSG@8 PS2, Line 8: : This will increase ME region size and reduce the BIOS region size. : : BUG:b:140665483 :
Remove extra tabs.
Done
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35304/1//COMMIT_MSG@9 PS1, Line 9: This will increase ME region size and reduce the BIOS regsion size.
region
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... PS3, Line 36: 0x17c8000 Does this fall on a boundary that is supported by the SPI flash to enable write protect?
Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... PS3, Line 36: 0x17c8000
Does this fall on a boundary that is supported by the SPI flash to enable write protect?
I use dump_fmap to check the WP_RO range, it shows start 0x01c00000 - end 0x02000000 that is same as before this change.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... PS3, Line 36: 0x17c8000
I use dump_fmap to check the WP_RO range, it shows start 0x01c00000 - end 0x02000000 that is same as […]
You are right. Sorry, I missed the offset from SI_BIOS completely.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... File src/mainboard/google/drallion/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/35304/3/src/mainboard/google/dralli... PS3, Line 36: 0x17c8000
You are right. Sorry, I missed the offset from SI_BIOS completely.
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35304 )
Change subject: mb/google/drallion: Update memory map ......................................................................
mb/google/drallion: Update memory map
This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483 TEST='compile successfully'
Signed-off-by: Ivy Jian ivy_jian@compal.corp-partner.google.com Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304 Reviewed-by: Mathew King mathewk@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, but someone else must approve Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 78b12bd..8bab919 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,26 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x402000 { + SI_ALL@0x0 0x438000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_ME@0x101000 0x2fd000 - SI_PDR(PRESERVE)@0x3fe000 0x4000 + SI_ME@0x101000 0x333000 + SI_PDR(PRESERVE)@0x434000 0x4000 } - SI_BIOS@0x402000 0x1bfe000 { - RW_DIAG@0x0 0x12ce000 { - RW_LEGACY(CBFS)@0x0 0x12be000 - DIAG_NVRAM@0x12be000 0x10000 + SI_BIOS@0x438000 0x1bc8000 { + RW_DIAG@0x0 0x1298000 { + RW_LEGACY(CBFS)@0x0 0x1288000 + DIAG_NVRAM@0x1288000 0x10000 } - RW_SECTION_A@0x12ce000 0x280000 { + RW_SECTION_A@0x1298000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x154e000 0x280000 { + RW_SECTION_B@0x1518000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17ce000 0x30000 { + RW_MISC@0x1798000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -33,7 +33,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x17fe000 0x400000 { + WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 {
-
EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
-
Ivy Jian (Code Review)
-
Mathew King (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)