Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7468
-gerrit
commit 040fe247ca935ce22c4c85c81bc32125125bcf1a Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Nov 10 19:12:53 2014 +0200
Intel FSP: Move to DYNAMIC_CBMEM
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms.
To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.
Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 ++ src/cpu/intel/fsp_model_406dx/Kconfig | 1 + src/mainboard/intel/cougar_canyon2/Kconfig | 2 -- src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 +++++++++-- src/soc/intel/broadwell/memmap.c | 7 +------ src/soc/intel/fsp_baytrail/Kconfig | 1 + 6 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..e323010 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -40,6 +40,8 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER + select BROKEN_CAR_MIGRATE + select DYNAMIC_CBMEM
config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 11a92a0..24be547 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE + select DYNAMIC_CBMEM
choice prompt "Rangeley CPU Stepping" diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 3b25161..cbad724 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select SUPERIO_SMSC_SIO1007 select ENABLE_VMX - select EARLY_CBMEM_INIT - select BROKEN_CAR_MIGRATE select INTEL_INT15 select VGA
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25..a95d736 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -243,9 +243,16 @@ static void pci_domain_set_resources(device_t dev) add_fixed_resources(dev, 6);
assign_resources(dev->link_list); +} + +unsigned long get_top_of_ram(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
- /* Leave some space for the HOB data above CBMem */ - set_top_of_ram((tomk - 2048) * 1024); + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); + tom -= 0x200000; /* 2MB for FSP HOB */ + return (unsigned long) tom; }
/* TODO We could determine how many PCIe busses we need in diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 698ff6b..046cc1d 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -23,7 +23,7 @@ #include <broadwell/pci_devs.h> #include <broadwell/systemagent.h>
-static unsigned long get_top_of_ram(void) +unsigned long get_top_of_ram(void) { /* * Base of DPR is top of usable DRAM below 4GiB. The register has @@ -39,8 +39,3 @@ static unsigned long get_top_of_ram(void)
return (unsigned long)tom; } - -void *cbmem_top(void) -{ - return (void *)get_top_of_ram(); -} diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index e9391c3..6ed0e20 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DYNAMIC_CBMEM + select BROKEN_CAR_MIGRATE select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT
-
Kyösti Mälkki