Change in coreboot[master]: soc/intel: Fix microcode loading

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Stefan Ott, Tim Wawrzynczak, Patrick Rudolph.
Hello Stefan Ott, build bot (Jenkins), Nico Huber, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/56153

to look at the new patch set (#2).

Change subject: soc/intel: Fix microcode loading
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soc/intel: Fix microcode loading

Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a
microcode blob with a total_size field set to 0. This appears to be
support for older chipsets, where the size was set to 0 and assumed to
be 2048 bytes. The fix is to change the result of the subtraction to a
signed type, and ensure the following comparison is done without
promoting the signed type to an unsigned one.

Resolves: https://ticket.coreboot.org/issues/313
Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622
Signed-off-by: Tim Wawrzynczak 
---
M src/cpu/intel/microcode/microcode.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56153/2