[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports

[Cliff Huang (Code Review)]

Attention is currently required from: Matt DeVillier, Sean Rhodes.

Cliff Huang has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email )

Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
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Patch Set 7:

(1 comment)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/85696/comment/cc832fd2_d10ba686?usp... :
PS5, Line 437: 	if (rp_type != PCIE_RP_PCH) {
> Initially, those methods are for rd3 internally. […]

If PCH RP also needs this support, the condition should be removed instead.