Change in coreboot[master]: src/soc/intel/cannonlake: add support for sata hotswap

[Jonas Löffelholz (Code Review)]

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: src/soc/intel/cannonlake: add support for sata hotswap
......................................................................

src/soc/intel/cannonlake: add support for sata hotswap

Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3ebbc5e..ac523d8 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -147,6 +147,7 @@
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];
    uint8_t SataPortsDevSlpResetConfig[8];
+	uint8_t SataPortsHotPlug[8];

/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
    uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a3b5588..c43d1b2 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -177,6 +177,10 @@
    		sizeof(params->SataPortsEnable));
    	memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
    		sizeof(params->SataPortsDevSlp));
+
+		memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
+			sizeof(params->SataPortsHotPlug));
+
 #if CONFIG(SOC_INTEL_COMETLAKE)
    	memcpy(params->SataPortsDevSlpResetConfig,
    		config->SataPortsDevSlpResetConfig,

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: src/soc/intel/cannonlake: add support for sata hotswap
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG@7 
PS1, Line 7: src/
remove src/

Change in coreboot[master]: soc/intel/cannonlake: add support for sata hotswap

[Jonas Löffelholz (Code Review)]

Hello Christian Walter, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42803

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: add support for sata hotswap
......................................................................

soc/intel/cannonlake: add support for sata hotswap

Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/2

Change in coreboot[master]: soc/intel/cannonlake: add support for sata hotswap

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: add support for sata hotswap
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG@8 
PS1, Line 8: 
Please describe what you are doing. Reading from the diff, you are hooking up an FSP UPD?

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetr...

[Jonas Löffelholz (Code Review)]

Hello build bot (Jenkins), Christian Walter, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42803

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree 	chip.h: add option to config 	fsp_params.c: copy sataHotPlug config to FSP UPD
......................................................................

soc/intel/cannonlake: make satahotplug user configurable via devicetree
    chip.h: add option to config
    fsp_params.c: copy sataHotPlug config to FSP UPD

Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/3

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetr...

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree 	chip.h: add option to config 	fsp_params.c: copy sataHotPlug config to FSP UPD
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG@8 
PS3, Line 8: 	chip.h: add option to config
Please add a blank line above to separate the commit message summary from the body by a blank line.

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG@8 
PS3, Line 8: chip.h: add option to config
           : 	fsp_params.c: copy sataHotPlug config to FSP UPD
Please format this as a list.

But just stating: *Hook up the FSP UPD* or something similar should be enough.

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetr...

[Jonas Löffelholz (Code Review)]

Jonas Löffelholz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree 	chip.h: add option to config 	fsp_params.c: copy sataHotPlug config to FSP UPD
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG@7 
PS1, Line 7: src/
> remove src/

Done

https://review.coreboot.org/c/coreboot/+/42803/1//COMMIT_MSG@8 
PS1, Line 8:
> Please describe what you are doing. […]

Done

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetree

[Jonas Löffelholz (Code Review)]

Hello build bot (Jenkins), Christian Walter, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42803

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree
......................................................................

soc/intel/cannonlake: make satahotplug user configurable via devicetree

Hook up the FSP UPD

Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/4

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetree

[Jonas Löffelholz (Code Review)]

Jonas Löffelholz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG@8 
PS3, Line 8: 	chip.h: add option to config
> Please add a blank line above to separate the commit message summary from the body by a blank line.

Done

https://review.coreboot.org/c/coreboot/+/42803/3//COMMIT_MSG@8 
PS3, Line 8: chip.h: add option to config
           : 	fsp_params.c: copy sataHotPlug config to FSP UPD
> Please format this as a list. […]

Done

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetree

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/cannonlake: make satahotplug user configurable via devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42803 )

Change subject: soc/intel/cannonlake: make satahotplug user configurable via devicetree
......................................................................

soc/intel/cannonlake: make satahotplug user configurable via devicetree

Hook up the FSP UPD

Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803
Reviewed-by: Christian Walter 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 57922e1..2923efc 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -147,6 +147,7 @@
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];
    uint8_t SataPortsDevSlpResetConfig[8];
+	uint8_t SataPortsHotPlug[8];

/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
    uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index bd2d7fc..3794ffd 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -297,6 +297,10 @@
    		sizeof(params->SataPortsEnable));
    	memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
    		sizeof(params->SataPortsDevSlp));
+
+		memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
+			sizeof(params->SataPortsHotPlug));
+
 #if CONFIG(SOC_INTEL_COMETLAKE)
    	memcpy(params->SataPortsDevSlpResetConfig,
    		config->SataPortsDevSlpResetConfig,