Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38795 )
Change subject: Kconfig: Guard CONFIGURABLE_RAMSTAGE ......................................................................
Kconfig: Guard CONFIGURABLE_RAMSTAGE
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it.
TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default.
Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38795/1
diff --git a/src/Kconfig b/src/Kconfig index 3742c04..4253ec7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,9 +354,13 @@ Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI).
+config HAVE_CONFIGURABLE_RAMSTAGE + bool + config CONFIGURABLE_RAMSTAGE bool "Enable a configurable ramstage." default y if ARCH_X86 + depends on HAVE_CONFIGURABLE_RAMSTAGE help A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38795 )
Change subject: Kconfig: Guard CONFIGURABLE_RAMSTAGE ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38795 )
Change subject: Kconfig: Guard CONFIGURABLE_RAMSTAGE ......................................................................
Kconfig: Guard CONFIGURABLE_RAMSTAGE
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it.
TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default.
Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/Kconfig b/src/Kconfig index 3742c04..4253ec7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,9 +354,13 @@ Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI).
+config HAVE_CONFIGURABLE_RAMSTAGE + bool + config CONFIGURABLE_RAMSTAGE bool "Enable a configurable ramstage." default y if ARCH_X86 + depends on HAVE_CONFIGURABLE_RAMSTAGE help A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step.
-
Martin Roth (Code Review) -
Subrata Banik (Code Review)