[M] Change in coreboot[master]: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params

[Kacper Stojek (Code Review)]

Attention is currently required from: Nico Huber, Michał Żygowski, Kacper Stojek, Paul Menzel, Angel Pons, Werner Zeh.

Hello build bot (Jenkins), Nico Huber, Michał Żygowski, Angel Pons, Lean Sheng Tan, Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72404

to look at the new patch set (#5).

Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
......................................................................

soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params

This commit eperates setting fsp debug params from the rest of code and
configures fsp serial port parameters. Other ports (0x3E8 and 0x2E8)
are ommited since elkhartlake only supports 0x3F8 and 0x2F8.

Signed-off-by: Michał Żygowski 
Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/romstage/fsp_params.c
2 files changed, 63 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/72404/5