[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 - coreboot-gerrit

5 Nov 2024


      Attention is currently required from: Hualin Wei, Karthik Ramasubramanian, Subrata Banik.
Eric Lai has posted comments on this change by Hualin Wei. ( https://review.coreboot.org/c/coreboot/+/84951?usp=email )
Change subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8
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Patch Set 3:
(1 comment)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84951/comment/0554658e_70315229?usp... :
PS3, Line 3: PcieRpLtrEnable
...
We made modifications based on CL84866,  and CL84866 defined this field. […]
Please add the related chain otherwise it will build failed.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418
Gerrit-Change-Number: 84951
Gerrit-PatchSet: 3
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Gerrit-Reviewer: Karthik Ramasubramanian kramasub@google.com
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