Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67527 )
Change subject: [WIP] mb/aaeon: Add Atomic Pi ......................................................................
[WIP] mb/aaeon: Add Atomic Pi
Working:
- UART 1 to receive spam - bootblock
Not working:
- Stupid FSP-M does not return
Untested:
- The rest
Change-Id: I1b50eccb2056ad44f0bd49230cd5add2b8a33bf7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/aaeon/Kconfig A src/mainboard/aaeon/Kconfig.name A src/mainboard/aaeon/atomic_pi/Kconfig A src/mainboard/aaeon/atomic_pi/Kconfig.name A src/mainboard/aaeon/atomic_pi/Makefile.inc A src/mainboard/aaeon/atomic_pi/acpi/ec.asl A src/mainboard/aaeon/atomic_pi/acpi/mainboard.asl A src/mainboard/aaeon/atomic_pi/acpi/superio.asl A src/mainboard/aaeon/atomic_pi/acpi_tables.c A src/mainboard/aaeon/atomic_pi/board_info.txt A src/mainboard/aaeon/atomic_pi/com_init.c A src/mainboard/aaeon/atomic_pi/devicetree.cb A src/mainboard/aaeon/atomic_pi/dsdt.asl A src/mainboard/aaeon/atomic_pi/gpio.c A src/mainboard/aaeon/atomic_pi/irqroute.c A src/mainboard/aaeon/atomic_pi/irqroute.h A src/mainboard/aaeon/atomic_pi/mainboard.c A src/mainboard/aaeon/atomic_pi/ramstage.c A src/mainboard/aaeon/atomic_pi/romstage.c A src/mainboard/aaeon/atomic_pi/spd/nanya.spd.hex A src/mainboard/aaeon/atomic_pi/w25q64.c 21 files changed, 674 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/67527/1
diff --git a/src/mainboard/aaeon/Kconfig b/src/mainboard/aaeon/Kconfig new file mode 100644 index 0000000..459af88 --- /dev/null +++ b/src/mainboard/aaeon/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_AAEON + +choice + prompt "Mainboard model" + +source "src/mainboard/aaeon/*/Kconfig.name" + +endchoice + +source "src/mainboard/aaeon/*/Kconfig" + +config MAINBOARD_VENDOR + default "AAEON" + +endif # VENDOR_AAEON diff --git a/src/mainboard/aaeon/Kconfig.name b/src/mainboard/aaeon/Kconfig.name new file mode 100644 index 0000000..08c6f14 --- /dev/null +++ b/src/mainboard/aaeon/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_AAEON + bool "AAEON" diff --git a/src/mainboard/aaeon/atomic_pi/Kconfig b/src/mainboard/aaeon/atomic_pi/Kconfig new file mode 100644 index 0000000..c9768cf --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/Kconfig @@ -0,0 +1,33 @@ +if BOARD_AAEON_ATOMIC_PI + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CACHE_MRC_SETTINGS + select DISABLE_HPET + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_BRASWELL + +# Looks like FSP uses a smaller CAR size for Cherry Trail +config DCACHE_RAM_SIZE + default 0x4000 + +config MAINBOARD_DIR + default "aaeon/atomic_pi" + +config MAINBOARD_PART_NUMBER + default "Atomic Pi" + +config ENABLE_BUILTIN_COM1 + default y + +config DIMM_MAX + default 1 + +config DIMM_SPD_SIZE + default 256 + +endif # BOARD_AAEON_ATOMIC_PI diff --git a/src/mainboard/aaeon/atomic_pi/Kconfig.name b/src/mainboard/aaeon/atomic_pi/Kconfig.name new file mode 100644 index 0000000..f18ac9b --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AAEON_ATOMIC_PI + bool "Atomic Pi" diff --git a/src/mainboard/aaeon/atomic_pi/Makefile.inc b/src/mainboard/aaeon/atomic_pi/Makefile.inc new file mode 100644 index 0000000..25c7bff --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + +ramstage-y += gpio.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +SPD_SOURCES = nanya diff --git a/src/mainboard/aaeon/atomic_pi/acpi/ec.asl b/src/mainboard/aaeon/atomic_pi/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/aaeon/atomic_pi/acpi/mainboard.asl b/src/mainboard/aaeon/atomic_pi/acpi/mainboard.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/aaeon/atomic_pi/acpi/superio.asl b/src/mainboard/aaeon/atomic_pi/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/aaeon/atomic_pi/acpi_tables.c b/src/mainboard/aaeon/atomic_pi/acpi_tables.c new file mode 100644 index 0000000..446e73e --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/acpi_tables.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_gnvs.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; +} diff --git a/src/mainboard/aaeon/atomic_pi/board_info.txt b/src/mainboard/aaeon/atomic_pi/board_info.txt new file mode 100644 index 0000000..d8e1778 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: AAEON +Board name: Atomic Pi +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/aaeon/atomic_pi/com_init.c b/src/mainboard/aaeon/atomic_pi/com_init.c new file mode 100644 index 0000000..12dfc9a --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/com_init.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> + +void bootblock_mainboard_early_init(void) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, M2)); +} diff --git a/src/mainboard/aaeon/atomic_pi/devicetree.cb b/src/mainboard/aaeon/atomic_pi/devicetree.cb new file mode 100644 index 0000000..a938fb9 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/devicetree.cb @@ -0,0 +1,114 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "0" + register "PcdEnableDma0" = "0" + register "PcdEnableDma1" = "0" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "1" # Disable SVID + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdPchSsicEnable" = "1" + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # Enable devices in PCI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 18.0 off end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 off end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 off end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on end # 8086 229c - LPC bridge + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/aaeon/atomic_pi/dsdt.asl b/src/mainboard/aaeon/atomic_pi/dsdt.asl new file mode 100644 index 0000000..3cced98 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +#define SDCARD_CD 81 /* Not used */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 +) +{ + #include <acpi/dsdt_top.asl> + + #include <acpi/platform.asl> + #include <acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <acpi/southcluster.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/aaeon/atomic_pi/gpio.c b/src/mainboard/aaeon/atomic_pi/gpio.c new file mode 100644 index 0000000..4fe49e0 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/gpio.c @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/gpio.h> +#include <stddef.h> + +/* TODO: Do not be lazy */ +#if 0 + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + GPIO_NC, /* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_NC, /* 02 MF_PLT_CLK1 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* 05 PWM0*/ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + GPIO_NC, /* 16 SDMMC1_CLK */ + GPIO_NC, /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + GPIO_NC, /* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + GPIO_NC, /* 23 SDMMC1_CMD */ + GPIO_NC, /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + GPIO_NC, /* 26 SDMMC1_D3_CD_B */ + GPIO_NC, /* 30 SDMMC3_D1 */ + GPIO_NC, /* 31 SDMMC3_CLK */ + GPIO_NC, /* 32 SDMMC3_D3 */ + GPIO_NC, /* 33 SDMMC3_D2 */ + GPIO_NC, /* 34 SDMMC3_CMD */ + GPIO_NC, /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + GPIO_NC, /* 60 SPI1_MISO */ + GPIO_NC, /* 61 SPI1_CS0_B */ + GPIO_NC, /* 62 SPI1_CLK */ + GPIO_NC, /* 63 MMC1_D6 */ + GPIO_NC, /* 64 SPI1_MOSI */ + GPIO_NC, /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + GPIO_NC, /* 67 MMC1_D4_SD_WE */ + GPIO_NC, /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), + /* 77 GPIO_ALERT */ + GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ + NATIVE_PU20K(1), /* 79 ILB_SERIRQ */ + NATIVE_PU20K(1), /* 80 USB_OC0_B */ + GPIO_NC, /* 81 SDMMC3_CD_B */ + Native_M1, /* 82 SPKR */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN, /* 84 SDMMC1_RCLK */ + GPIO_NC, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + GPO_FUNC(P_20K_H, 1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPO_FUNC(P_20K_H, 1), /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + NATIVE_PD20K(2), /* 30 MF_HDA_CLK */ + NATIVE_PD20K(2), /* 31 GPIO_SW31/MF_HDA_RSTB */ + NATIVE_PD20K(2), /* 32 GPIO_SW32/MF_HDA_SDI0 */ + NATIVE_PD20K(2), /* 33 MF_HDA_SDO */ + GPO_FUNC(P_20K_L, 1), /* 34 MF_HDA_DOCKRSTB */ + NATIVE_PD20K(2), /* 35 MF_HDA_SYNC */ + NATIVE_PD20K(2), /* 36 GPIO_SW36/MF_HDA_SDI1 */ + GPIO_INPUT_PD_20K, /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + GPIO_NC, /* 47 I2C6_SDA */ + GPIO_NC, /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + GPIO_NC, /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + GPIO_NC, /* 60 I2C1_SDA */ + GPIO_NC, /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + GPIO_NC, /* 63 I2C1_SCL */ + GPIO_NC, /* 64 I2C3_SDA */ + GPIO_NC, /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_NC, /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + NATIVE_PU20K(1), /* 79 MF_SMB_ALERTB */ + GPIO_NC, /* 80 SATA_GP3 */ + NATIVE_PU20K(1), /* 81 MF_SMB_CLK */ + NATIVE_PU20K(1), /* 82 MF_SMB_DATA */ + GPIO_NC, /* 90 PCIE_CLKREQ0B */ + GPIO_NC, /* 91 PCIE_CLKREQ1B */ + GPIO_NC, /* 92 GP_SSP_2_CLK */ + GPIO_NC, /* 93 PCIE_CLKREQ2B */ + GPIO_NC, /* 94 GP_SSP_2_RXD */ + GPIO_NC, /* 95 PCIE_CLKREQ3B */ + GPIO_NC, /* 96 GP_SSP_2_FS */ + GPIO_NC, /* 97 GP_SSP_2_TXD */ + GPIO_END +}; + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, P_20K_L, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(P_20K_L, 1), /* 16 SEC_GPIO_SUS10 */ + NATIVE_PD20K(1), /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L15, P_20K_H, non_maskable, en_edge_rx_data, NA, + SMI), /* 18 GPIO_SUS7 */ + NATIVE_PD20K(1), /* 19 GPIO_SUS1 */ + GPIO_INPUT_PU_20K, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, P_20K_L, non_maskable, en_edge_rx_data, NA, + NA), /* 21 SEC_GPIO_SUS11 */ + NATIVE_PU20K(1), /* 22 GPIO_SUS4 */ + GPI(trig_level_high, L3, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 23 SEC_GPIO_SUS8 */ + NATIVE_PU20K(1), /* 24 GPIO_SUS2 */ + GPI(trig_edge_low, L14, P_20K_H, non_maskable, en_edge_rx_data, NA, + SCI), /* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_INPUT_PD_20K, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + GPIO_NC, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + NATIVE_TX_RX_EN, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + GPIO_NC, /* 63 PANEL1_BKLTCTL */ + GPIO_NC, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU1K_M1, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + GPIO_NC, /* 69 PANEL1_VDDEN */ + GPIO_NC, /* 70 PANEL1_BKLTEN */ + NATIVE_PU1K_M1, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + NATIVE_PU20K(1), /* 00 PMU_SLP_S3_B */ + NATIVE_PU20K(1), /* 01 PMU_BATLOW_B */ + NATIVE_PU20K(1), /* 02 SUS_STAT_B */ + NATIVE_PU20K(1), /* 03 PMU_SLP_S0IX_B */ + NATIVE_PD20K(1), /* 04 PMU_AC_PRESENT */ + NATIVE_PU20K(1), /* 05 PMU_PLTRST_B */ + NATIVE_PD20K(1), /* 06 PMU_SUSCLK */ + NATIVE_PU20K(1), /* 07 PMU_SLP_LAN_B */ + NATIVE_PU20K(1), /* 08 PMU_PWRBTN_B */ + NATIVE_PU20K(1), /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC_TX_RX(en_rx_data << 2, 1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +#endif + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return NULL; //&gpio_config; +} diff --git a/src/mainboard/aaeon/atomic_pi/irqroute.c b/src/mainboard/aaeon/atomic_pi/irqroute.c new file mode 100644 index 0000000..6f9823a --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/aaeon/atomic_pi/irqroute.h b/src/mainboard/aaeon/atomic_pi/irqroute.h new file mode 100644 index 0000000..1cde33e --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/irqroute.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, D, B, C, A), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, C, A, A) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/aaeon/atomic_pi/mainboard.c b/src/mainboard/aaeon/atomic_pi/mainboard.c new file mode 100644 index 0000000..3c9c45c --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/mmio.h> +#include <device/device.h> +#include <soc/iomap.h> + +#define BIOS_CONTROL_REG 0xFC +#define BIOS_CONTROL_WPD (1 << 0) + +static void mainboard_enable(struct device *dev) +{ + volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG); + + /* Set Bios Write Protect Disable bit to allow saving MRC cache */ + write8(addr, read8(addr) | BIOS_CONTROL_WPD); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/aaeon/atomic_pi/ramstage.c b/src/mainboard/aaeon/atomic_pi/ramstage.c new file mode 100644 index 0000000..61be3bb --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + params->PcdTurboMode = 1; +} diff --git a/src/mainboard/aaeon/atomic_pi/romstage.c b/src/mainboard/aaeon/atomic_pi/romstage.c new file mode 100644 index 0000000..278a6b1 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cbfs.h> +#include <lib.h> +#include <soc/romstage.h> +#include <spd.h> +#include <spd_bin.h> + +static void *get_spd_pointer(int *dual) +{ + size_t spd_file_len; + char *spd_file = cbfs_map("spd.bin", &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_PAGE_LEN) + die("Missing SPD data."); + + return spd_file; +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + void *spd_content; + int dual_channel = 0; + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(&dual_channel); + if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_PAGE_LEN); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + memory_params->PcdMemChannel0Config = 1; + memory_params->PcdMemChannel1Config = 2; + } + + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)spd_content; +} diff --git a/src/mainboard/aaeon/atomic_pi/spd/nanya.spd.hex b/src/mainboard/aaeon/atomic_pi/spd/nanya.spd.hex new file mode 100644 index 0000000..6b2e10f --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/spd/nanya.spd.hex @@ -0,0 +1,16 @@ +92 11 0b 02 04 19 00 02 03 11 01 08 0a 00 fc 00 +69 78 69 3c 69 11 18 81 20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0f 01 22 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 01 98 05 15 38 91 22 6d 85 0b 23 +39 39 30 35 35 39 35 2d 30 31 30 2e 41 30 30 4c +46 20 00 00 83 0b 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a diff --git a/src/mainboard/aaeon/atomic_pi/w25q64.c b/src/mainboard/aaeon/atomic_pi/w25q64.c new file mode 100644 index 0000000..d19b371 --- /dev/null +++ b/src/mainboard/aaeon/atomic_pi/w25q64.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI VSCC configuration W25Q64FW. + */ +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct vscc_config spi_config = { + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_vscc_config(struct vscc_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}
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Angel Pons (Code Review)