Attention is currently required from: Marshall Dawson, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60142 )
Change subject: soc/amd/stoneyridge: split southbridge code ......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/stoneyridge/fch.c:
https://review.coreboot.org/c/coreboot/+/60142/comment/0dfe6347_10938094 PS1, Line 175: if (gnvs) {
There's probably no need to have them in GNVS or update on S3 resume path. […]
I agree that the AOAC and XHCI firmware address information don't need to be in GNVS and that it would be good to move them out of there. Since this patch is only about splitting the fch code in a bootblock and a ramstage part and i haven't gotten around to figure out what's exactly needed to get the stoneyridge device to boot to the linux desktop to verify that this sort of things still works, i'd add a patch on top of this patch train that adds a comment that this should eventually be done without using gnvs. see CB:60196
From the ACPI code, i'd assume that the XHCI controller needs to have it firmware reloaded when going from D3 to D0, but i'm not sure if that's a hardware requirement or just how things were done. Same problem here that i can't easily validate changes around this right now.
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Felix Held (Code Review)