Attention is currently required from: Felix Singer, Angel Pons, Michael Niewöhner, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56664 )
Change subject: soc/intel/cannonlake: Report correct latencies for C states ......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56664/comment/9142b3d5_10fb1787 PS1, Line 7: correct
As per which source of information?
What we program to the hardware, actually. cf. CB:56662, and skylake/ (it's the same silicon, basically)
The programmed values are given by the SKL/KBL/CFL/CML BWG.
https://review.coreboot.org/c/coreboot/+/56664/comment/d0dd03b1_40007b2f PS1, Line 8:
tested? if yes, how?
Well, we do run everything on our current hardware target Roda/RW14. But I don't know if this counts as testing. Most of the values in this table are never read (see below, only C1E C6_LONG_LAT, C7_LONG_LAT and C10 are). And I don't know if Linux consumes the values. The whole code here seems a bit overengineered. Which makes it hard to use any- thing but the recommended values, blindly.
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Nico Huber (Code Review)