Alexander Couzens (lynxis@fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8400
-gerrit
commit 08a838c02755b066e2279c60b1f9d99da6f821c5 Author: Alexander Couzens lynxis@fe80.eu Date: Sun Feb 8 12:00:28 2015 +0100
add amdtool: an opponent to inteltool
This first version only dumps the index register space for AMD 14h.
Change-Id: I86627ef319f9732f9188161551bdcd0605c4c112 Signed-off-by: Alexander Couzens lynxis@fe80.eu --- util/amdtool/Makefile | 39 ++++++++++++ util/amdtool/amdtool.c | 38 ++++++++++++ util/amdtool/amdtool.h | 37 ++++++++++++ util/amdtool/cmn.c | 160 +++++++++++++++++++++++++++++++++++++++++++++++++ util/amdtool/cmn.h | 42 +++++++++++++ util/amdtool/index.c | 98 ++++++++++++++++++++++++++++++ 6 files changed, 414 insertions(+)
diff --git a/util/amdtool/Makefile b/util/amdtool/Makefile new file mode 100644 index 0000000..21350c4 --- /dev/null +++ b/util/amdtool/Makefile @@ -0,0 +1,39 @@ +## +## Makefile for amd_10h_tool +## +## Copyright (C) 2014 Alexander Couzens lynxis@fe80.eu +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +CC = gcc +CFLAGS = -O2 -Wall -W -std=c99 +PROGRAM = amdtool +INSTALL = /usr/bin/install +PREFIX = /usr/local +LDFLAGS = -lpci + +all: $(PROGRAM) + +$(PROGRAM): amdtool.o cmn.o index.o + $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + +clean: + rm *.o $(PROGRAM) + +%.o: %.c + $(CC) $(CFLAGS) -c $^ -I. -o $@ diff --git a/util/amdtool/amdtool.c b/util/amdtool/amdtool.c new file mode 100644 index 0000000..f6ef7ac --- /dev/null +++ b/util/amdtool/amdtool.c @@ -0,0 +1,38 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens lynxis@fe80.eu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdio.h> +#include <stdint.h> +#include <pci/pci.h> + +#include "amdtool.h" +#include "cmn.h" + +int main() { + struct pci_access *pci_acc = pci_alloc(); + struct pci_dev *dev = NULL; + + pci_init(pci_acc); + dev = pci_get_dev(pci_acc, 0, 0, 0, 0); + pci_fill_info(dev, PCI_FILL_CLASS|PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); + + print_index(dev); + + return 0; +} diff --git a/util/amdtool/amdtool.h b/util/amdtool/amdtool.h new file mode 100644 index 0000000..b9a7eb9 --- /dev/null +++ b/util/amdtool/amdtool.h @@ -0,0 +1,37 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens lynxis@fe80.eu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef AMDTOOL_H_ +#define AMDTOOL_H_ + +#include <stdint.h> + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + +#define PCI_VENDOR_ID_AMD 0x1022 + +#define PCI_VENDOR_ID_AMD_NB_14H 0x1510 + +typedef struct { uint32_t addr; int size; char *name; } io_register_t; + +void print_index(struct pci_dev *nb); + +#endif /* AMDTOOL_H_ */ diff --git a/util/amdtool/cmn.c b/util/amdtool/cmn.c new file mode 100644 index 0000000..4795e5a --- /dev/null +++ b/util/amdtool/cmn.c @@ -0,0 +1,160 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdint.h> +#include <pci/pci.h> + +#define NBMISC_INDEX 0x60 +#define NBPCIE_INDEX 0xE0 +#define NBMC_INDEX 0xE8 +#define NBHTIU_INDEX 0x94 + +#define pci_read_config32 pci_read_long +#define pci_read_config8 pci_read_byte +#define pci_write_config32 pci_write_long +#define pci_write_config8 pci_write_byte + +static u32 nb_read_index(struct pci_dev * dev, u32 index_reg, u32 index) +{ + pci_write_config32(dev, index_reg, index); + return pci_read_config32(dev, index_reg + 0x4); +} + +static void nb_write_index(struct pci_dev * dev, u32 index_reg, u32 index, u32 data) +{ + pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg + 0x4, data); +} + + +u32 nbmisc_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMISC_INDEX, (index)); +} + +void nbmisc_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); +} + +u32 nbpcie_p_read_index(struct pci_dev * dev, u32 index) +{ + return nb_read_index((dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_p_write_index(struct pci_dev * dev, u32 index, u32 data) +{ + nb_write_index((dev), NBPCIE_INDEX, (index), (data)); +} + +u32 nbpcie_ind_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_ind_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); +} + +u32 htiu_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); +} + +void htiu_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); +} + +u32 nbmc_read_index(struct pci_dev * nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMC_INDEX, (index)); +} + +void nbmc_write_index(struct pci_dev * nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); +} + +void set_nbcfg_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = pci_read_config32(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config32(nb_dev, reg_pos, reg); + } +} + +void set_nbcfg_enable_bits_8(struct pci_dev * nb_dev, u32 reg_pos, u8 mask, u8 val) +{ + u8 reg_old, reg; + reg = reg_old = pci_read_config8(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config8(nb_dev, reg_pos, reg); + } +} + +void set_nbmc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmc_write_index(nb_dev, reg_pos, reg); + } +} + +void set_htiu_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = htiu_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + htiu_write_index(nb_dev, reg_pos, reg); + } +} + +void set_nbmisc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmisc_write_index(nb_dev, reg_pos, reg); + } +} + +void set_pcie_enable_bits(struct pci_dev * dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); + } +} diff --git a/util/amdtool/cmn.h b/util/amdtool/cmn.h new file mode 100644 index 0000000..b78254f --- /dev/null +++ b/util/amdtool/cmn.h @@ -0,0 +1,42 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef CMN_H__H_ +#define CMN_H__H_ + +struct pci_dev; + +u32 nbmisc_read_index(struct pci_dev * nb_dev, u32 index); +void nbmisc_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 nbpcie_p_read_index(struct pci_dev * dev, u32 index); +void nbpcie_p_write_index(struct pci_dev * dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(struct pci_dev * nb_dev, u32 index); +void nbpcie_ind_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 htiu_read_index(struct pci_dev * nb_dev, u32 index); +void htiu_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +u32 nbmc_read_index(struct pci_dev * nb_dev, u32 index); +void nbmc_write_index(struct pci_dev * nb_dev, u32 index, u32 data); +void set_nbcfg_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbcfg_enable_bits_8(struct pci_dev * nb_dev, u32 reg_pos, u8 mask, u8 val); +void set_nbmc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_htiu_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_nbmisc_enable_bits(struct pci_dev * nb_dev, u32 reg_pos, u32 mask, u32 val); +void set_pcie_enable_bits(struct pci_dev * dev, u32 reg_pos, u32 mask, u32 val); + +#endif /* CMN_H__H_ */ diff --git a/util/amdtool/index.c b/util/amdtool/index.c new file mode 100644 index 0000000..b2d870e --- /dev/null +++ b/util/amdtool/index.c @@ -0,0 +1,98 @@ +/* + * amdtool - dump all registers on an AMD CPU + chipset based system. + * + * Copyright (C) 2015 Alexander Couzens lynxis@fe80.eu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdio.h> +#include <stdint.h> +#include <pci/pci.h> + +#include "amdtool.h" +#include "cmn.h" + +/* AMD 14h documentation based on + * BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors + * 43170 Rev 3.13 - February 17, 2012 + */ + +static const io_register_t amd_14_e4[] = { + /* IO Link */ + { 0x01010002, 4, "IO Link Hardware Debug"}, + { 0x01010010, 4, "IO Link Control 1"}, + { 0x01010011, 4, "IO Link Config Control"}, + { 0x0101001C, 4, "IO Link Control 2"}, + { 0x01010020, 4, "IO Link Chip Interface Control"}, + { 0x01010040, 4, "IO Link Phy Control"}, + { 0x010100B0, 4, "IO Link Strap Control"}, + { 0x010100C0, 4, "IO Link Strap Miscellaneous"}, + { 0x010100C1, 4, "IO Link Strap Miscellaneous"}, + /* Impedance Controller Registers */ + { 0x01088071, 4, "Receiver Impedance Adjustment"}, + { 0x01088072, 4, "Transmitter Impedance Adjustment"}, + /* TODO: PIF Registers */ + /* Wrapper Registers */ + { 0x01300000, 4, "BIF Core Feature Enable"}, + { 0x01300002, 4, "Link Speed Control"}, + { 0x01300080, 4, "Link Configuration"}, + { 0x01300800, 4, "Device 8 Link Training Control"}, + { 0x01300803, 4, "Device 8 Link De-emphasis Control"}, + { 0x01300900, 4, "Device 4 Link Training Control"}, + { 0x01300903, 4, "Device 4 Link De-emphasis Control"}, + { 0x01300a00, 4, "Device 5 Link Training Control"}, + { 0x01300a03, 4, "Device 5 Link De-emphasis Control"}, + { 0x01300b00, 4, "Device 6 Link Training Control"}, + { 0x01300b03, 4, "Device 6 Link De-emphasis Control"}, + { 0x01300c00, 4, "Device 7 Link Training Control"}, + { 0x01300c03, 4, "Device 7 Link De-emphasis Control"}, + { 0x01308002, 4, "Subsystem and Subvendor ID Control"}, + { 0x01308011, 4, "Link Transmit Clock Gating Control"}, + { 0x01308012, 4, "Link Transmit Clock Gating Control 2"}, + { 0x01308013, 4, "Transmit Clock PLL Control"}, + { 0x01308016, 4, "Link Clock Switching Control"}, + { 0x01308021, 4, "Transmitter Lane Mux"}, + { 0x01308022, 4, "Receiver Lane Mux"}, + { 0x01308023, 4, "Lane Enable"}, + { 0x01308025, 4, "Lane Mux Power Sequence Control 0"}, + { 0x01308031, 4, "Lane Counter Status"}, + { 0x01308060, 4, "Soft Reset Command 0"}, + { 0x01308061, 4, "Soft Reset Command 1"}, + { 0x01308062, 4, "Soft Reset Control 0"}, + { 0x013080F0, 4, "BIOS Timer"}, + { 0x013080F1, 4, "BIOS Timer Control"}, +}; + +void print_index(struct pci_dev *nb) +{ + int index_size = 0; + const io_register_t *index; + + printf("=== Index Register Space ===\n"); + switch (nb->device_id) { + case PCI_VENDOR_ID_AMD_NB_14H: + index_size = ARRAY_SIZE(amd_14_e4); + index = amd_14_e4; + break; + default: + printf("Unsupported Northbridge pci %x\n", nb->device_id); + return; + break; + } + + for (int i=0; i < index_size; i++) { + printf("0x%08x = 0x%08x - %s\n", index[i].addr, nbpcie_p_read_index(nb, index[i].addr), index[i].name); + } +}
-
Alexander Couzens