Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 )

Change subject: soc/mediatek/mt8195: fix GPIO register offset
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55163/comment/6f65cc49_320e2fa4 
PS1, Line 9: Fix GPIO pu/pd offset.
> Do you have a reference for these offsets so we can know it's now correct? […]

In file MT8195 Register Map_V0.2 -1.pdf
(https://drive.google.com/drive/folders/12qTn0CBvrmV1UNyJiWNEJGEpj_OGGfzl?res...)
chapter: 3.2 GPIO Controller (page3272)

control register name: 
    PUPD_CFG0
    PU_CFG0

offset should be fix is which bit control GPIO PUPD/PU

Detail:
3.2.2 IOCGF_LM 
    PUPD_CFG0 (page:3347)
    PU_CFG0    (page:3348)
3.2.3 IOCGF_BL
    PU_CFG0 (page:3373)
3.2.4 IOCGF_BM
    PU_CFG0 (page:3400)
3.2.5 IOCGF_BR
    PUPD_CFG0 (page:3428)
    PU_CFG0 (page:3432)
3.2.6 IOCGF_RB
    PUPD_CFG0 (page:3456)
3.2.7 IOCGF_TL
    PUPD_CFG0 (page:3473)
    PU_CFG0 (page:3475)