Change in coreboot[master]: nb/intel/gm45: Remove UMA alignment optimization

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21847

Change subject: nb/intel/gm45: Remove UMA alignment optimization
......................................................................

nb/intel/gm45: Remove UMA alignment optimization

This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.

Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber 
---
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/raminit.c
2 files changed, 3 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21847/1

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 3cb7d11..8215979 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -71,7 +71,7 @@
 static void mch_domain_read_resources(device_t dev)
 {
    u64 tom, touud;
-	u32 tomk, tolud, uma_sizek = 0, usable_tomk;
+	u32 tomk, tolud, uma_sizek = 0;
    u32 pcie_config_base, pcie_config_size;

/* Total Memory 2GB example:
@@ -130,16 +130,12 @@
    	uma_sizek = gms_sizek + gsm_sizek;
    }

-	usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
-	if (tomk - usable_tomk > (16 << 10))
-		usable_tomk = tomk;
-
-	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
+	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);

/* Report the memory regions */
    ram_resource(dev, 3, 0, legacy_hole_base_k);
    ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
-		     (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
+		     (tomk - (legacy_hole_base_k + legacy_hole_size_k)));

/*
     * If >= 4GB installed then memory from TOLUD to 4GB
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index d2da3b0..a44e397 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1241,10 +1241,6 @@
    		printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);

uma_sizem = (gms_sizek + gsm_sizek) >> 10;
-			/* Further reduce MTRR usage if it costs use less than
-			   16 MiB.  */
-			if (ALIGN_UP(uma_sizem, 64) - uma_sizem <= 16)
-				uma_sizem = ALIGN_UP(uma_sizem, 64);
    	}
    }