Change in coreboot[master]: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63024 )

Change subject: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields
......................................................................

sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields

Clang complains about this.

Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024
Tested-by: build bot (Jenkins) 
Reviewed-by: Elyes Haouas 
---
M src/southbridge/intel/i82801ix/chip.h
M src/southbridge/intel/i82801jx/chip.h
2 files changed, 13 insertions(+), 13 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Elyes Haouas: Looks good to me, approved

diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index 3ec68ae..ec7b977 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -55,17 +55,17 @@

/* IDE configuration */
    uint8_t sata_port_map : 6;
-	int sata_clock_request : 1;
-	int sata_traffic_monitor : 1;
+	unsigned int sata_clock_request : 1;
+	unsigned int sata_traffic_monitor : 1;

-	int c4onc3_enable:1;
-	int c5_enable : 1;
-	int c6_enable : 1;
+	unsigned int c4onc3_enable:1;
+	unsigned int c5_enable : 1;
+	unsigned int c6_enable : 1;

-	int throttle_duty : 3;
+	unsigned int throttle_duty : 3;

/* Bit mask to tell whether a PCIe slot is implemented as slot. */
-	int pcie_slot_implemented : 6;
+	unsigned int pcie_slot_implemented : 6;

/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
    struct {
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index e9632d2..ae31d4f 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -42,16 +42,16 @@

/* IDE configuration */
    uint8_t sata_port_map : 6;
-	int sata_clock_request : 1;
+	unsigned int sata_clock_request : 1;

-	int c4onc3_enable:1;
-	int c5_enable : 1;
-	int c6_enable : 1;
+	unsigned int c4onc3_enable:1;
+	unsigned int c5_enable : 1;
+	unsigned int c6_enable : 1;

-	int throttle_duty : 3;
+	unsigned int throttle_duty : 3;

/* Bit mask to tell whether a PCIe slot is implemented as slot. */
-	int pcie_slot_implemented : 6;
+	unsigned int pcie_slot_implemented : 6;

/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
    struct {