Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table - coreboot-gerrit

8 May 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 )
Change subject: soc/amd/cezanne: Generate PCI routing table
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Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51556/comment/6ea0462a_cab0c32b 
PS10, Line 10:
...
The diff includes a comment referencing a bug. […]
It says in the comment `Enable GNB IO-APIC`.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326
Gerrit-Change-Number: 51556
Gerrit-PatchSet: 10
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