Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28264
Change subject: [WIP]mb/asus/p5qc: Add mainboard ......................................................................
[WIP]mb/asus/p5qc: Add mainboard
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards
Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress)
Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR2 DIMMs in only the uneven slots - DDR3 fails to get initialised during JEDEC init (those are uneven slots, which might be the same problem as the previous one)
Untested: - PCIe x1 ports (expected to work) - sound (expected to work)
TODO: add documentation
Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- A src/mainboard/asus/p5qc/Kconfig A src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/Makefile.inc A src/mainboard/asus/p5qc/acpi/ec.asl A src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl A src/mainboard/asus/p5qc/acpi/platform.asl A src/mainboard/asus/p5qc/acpi/superio.asl A src/mainboard/asus/p5qc/acpi_tables.c A src/mainboard/asus/p5qc/board_info.txt A src/mainboard/asus/p5qc/cmos.default A src/mainboard/asus/p5qc/cmos.layout A src/mainboard/asus/p5qc/config_seabios A src/mainboard/asus/p5qc/cstates.c A src/mainboard/asus/p5qc/devicetree.cb A src/mainboard/asus/p5qc/dsdt.asl A src/mainboard/asus/p5qc/gpio.c A src/mainboard/asus/p5qc/hda_verb.c A src/mainboard/asus/p5qc/romstage.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/i82801jx/i82801jx.h 20 files changed, 781 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28264/1
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig new file mode 100644 index 0000000..605dfd7 --- /dev/null +++ b/src/mainboard/asus/p5qc/Kconfig @@ -0,0 +1,51 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83667HG_A + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + +config MAINBOARD_DIR + string + default "asus/p5qc" + +config MAINBOARD_PART_NUMBER + string + default "P5QC" + +config MAX_CPUS + int + default 4 + +# The MARVEL IDE controller delays SeaBIOS a lot and results in an unbootable +# bogus disk. Compiling SeaBIOS without ATA support is a workaround. + +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + +endif # BOARD_ASUS_P5QC diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name new file mode 100644 index 0000000..d764867 --- /dev/null +++ b/src/mainboard/asus/p5qc/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QC + bool "P5QC" diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc new file mode 100644 index 0000000..630abda --- /dev/null +++ b/src/mainboard/asus/p5qc/Makefile.inc @@ -0,0 +1,15 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-y += cstates.c +romstage-y += gpio.c diff --git a/src/mainboard/asus/p5qc/acpi/ec.asl b/src/mainboard/asus/p5qc/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..e8cb26e --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + + Package() { 0x0001ffff, 0, 0, 0x11}, + Package() { 0x0001ffff, 1, 0, 0x12}, + Package() { 0x0001ffff, 2, 0, 0x13}, + Package() { 0x0001ffff, 3, 0, 0x10}, + + Package() { 0x0002ffff, 0, 0, 0x12}, + Package() { 0x0002ffff, 1, 0, 0x13}, + Package() { 0x0002ffff, 2, 0, 0x10}, + Package() { 0x0002ffff, 3, 0, 0x11}, + + Package() { 0x0003ffff, 0, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, _SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, _SB.PCI0.LPCB.LNKB, 0}, + + Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5qc/acpi/superio.asl b/src/mainboard/asus/p5qc/acpi/superio.asl new file mode 100644 index 0000000..48e70a7 --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ \ No newline at end of file diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c new file mode 100644 index 0000000..d609a0e --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi_tables.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5qc/board_info.txt b/src/mainboard/asus/p5qc/board_info.txt new file mode 100644 index 0000000..111f2e4 --- /dev/null +++ b/src/mainboard/asus/p5qc/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QC/ +ROM package: SOP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5qc/cmos.default b/src/mainboard/asus/p5qc/cmos.default new file mode 100644 index 0000000..ccdb7c8 --- /dev/null +++ b/src/mainboard/asus/p5qc/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout new file mode 100644 index 0000000..e1d4e2b --- /dev/null +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +#432 554 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +1024 144 r 0 recv_enable_results +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5qc/config_seabios b/src/mainboard/asus/p5qc/config_seabios new file mode 100644 index 0000000..1cc1982 --- /dev/null +++ b/src/mainboard/asus/p5qc/config_seabios @@ -0,0 +1 @@ +# CONFIG_ATA is not set \ No newline at end of file diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c new file mode 100644 index 0000000..aa7214d --- /dev/null +++ b/src/mainboard/asus/p5qc/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801jx/i82801jx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/devicetree.cb new file mode 100644 index 0000000..b1e9a48 --- /dev/null +++ b/src/mainboard/asus/p5qc/devicetree.cb @@ -0,0 +1,123 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit damien@zamaudio.com +# Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 on end # PEG + device pci 2.0 off end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.5 on end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + # Global registers + irq 0x2a = 0x00 + irq 0x2c = 0x22 + irq 0x2d = 0x00 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI1 + device pnp 2e.107 off end # GIPO6 + device pnp 2e.207 off end # GIPO7 + device pnp 2e.307 on # GIPO8 + irq 0xe4 = 0xfb + irq 0xe5 = 0x02 + end + device pnp 2e.407 off end # GIPO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO 1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xfe = 0x07 + end + device pnp 2e.309 on end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # 3VSBSW# enable + irq 0xe5 = 0x02 + irq 0xf2 = 0xfc + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + # IRQ purposefully not assigned to prevent lockups + end + device pnp 2e.c on end # PECI + device pnp 2e.d on end # VID_BUSSEL + device pnp 2e.f on end # GPIO_PP_OD + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end # IDE + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl new file mode 100644 index 0000000..4888b9c --- /dev/null +++ b/src/mainboard/asus/p5qc/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5qc/gpio.c b/src/mainboard/asus/p5qc/gpio.c new file mode 100644 index 0000000..fdafafc --- /dev/null +++ b/src/mainboard/asus/p5qc/gpio.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c new file mode 100644 index 0000000..22832bb --- /dev/null +++ b/src/mainboard/asus/p5qc/hda_verb.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19d60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214d20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01447130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c new file mode 100644 index 0000000..eb534ca --- /dev/null +++ b/src/mainboard/asus/p5qc/romstage.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83667hg-a/w83667hg-a.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> +#include <northbridge/intel/x4x/iomap.h> +#include <timestamp.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Set default GPIOs on superio: TODO (here or in ramstage) */ + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); + + /* TODO? */ + RCBA32(RCBA_CG) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x00000038; +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + /* HW EC */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); + /* ????? */ + pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); +} + +void mainboard_romstage_entry(unsigned long bist) +{ + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; + u8 boot_path = 0; + u8 s3_resume; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 9d37ada..6715f44 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -296,6 +296,7 @@ min_tCLK = MAX(min_tCLK, TCK_533MHZ); break; case 3: /* Only on P45 */ + case 0: min_tCLK = MAX(min_tCLK, TCK_666MHZ); break; } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2e2d719..3c09746 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -99,6 +99,16 @@ #define D31F0_PIRQH_ROUT 0x6b #define D31F0_LPC_IODEC 0x80 #define D31F0_LPC_EN 0x82 +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define D31F0_GEN1_DEC 0x84 #define D31F0_GEN2_DEC 0x88 #define D31F0_GEN3_DEC 0x8c
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Arthur Heymans (Code Review)