Change in coreboot[master]: riscv: simplify timer interrupt handling

[Philipp Hug (Code Review)]

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/29340 )

Change subject: riscv: simplify timer interrupt handling
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riscv: simplify timer interrupt handling

Just disable the timer interrupt and notify supervisor.
To receive another timer interrupt just set timecmp and
enable machine mode timer interrupt again.

TEST=Run linux on sifive unleashed

Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd
Signed-off-by: Philipp Hug 
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M src/arch/riscv/trap_handler.c
1 file changed, 45 insertions(+), 84 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/2