Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
mb/google/zork: Add INT[E-H] to FCH PIR
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019 TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 --- M src/mainboard/google/zork/mainboard.c 1 file changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48664/1
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index dce2eaf..824a87d 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -76,7 +76,14 @@
/* * This controls the device -> IRQ routing. - * The PIC values are limited to 0,1, 3 - 12, 14, 15. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 <- ec/google/chromeec/acpi/superio.asl + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + * 12: i8042 <- ec/google/chromeec/acpi/superio.asl */ static const struct fch_irq_routing { uint8_t intr_index; @@ -84,9 +91,14 @@ uint8_t apic_irq_num; } fch_pirq[] = { { PIRQ_A, 6, 16 }, - { PIRQ_B, 6, 17 }, + { PIRQ_B, 13, 17 }, { PIRQ_C, 14, 18 }, { PIRQ_D, 15, 19 }, + { PIRQ_E, 15, 20 }, + { PIRQ_F, 14, 21 }, + { PIRQ_G, 13, 22 }, + { PIRQ_H, 6, 23 }, + { PIRQ_SCI, 9, 9 }, { PIRQ_EMMC, 5, 5 }, { PIRQ_GPIO, 7, 7 },
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
Patch Set 1:
should this change also be applied to amd/mandolin?
Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
Patch Set 1: Code-Review+1
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
Patch Set 1:
Patch Set 1:
should this change also be applied to amd/mandolin?
We can in a follow up. Though in practice it doesn't matter. The ACPI entry defines the possible IRQs, and the kernel will choose one of those if it's not already configured: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
Patch Set 1: Code-Review+2
Patch Set 1:
Patch Set 1:
should this change also be applied to amd/mandolin?
We can in a follow up. Though in practice it doesn't matter. The ACPI entry defines the possible IRQs, and the kernel will choose one of those if it's not already configured: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
I'm ok with doing that as a follow-up patch
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48664 )
Change subject: mb/google/zork: Add INT[E-H] to FCH PIR ......................................................................
mb/google/zork: Add INT[E-H] to FCH PIR
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019 TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/mainboard.c 1 file changed, 14 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Nikolai Vyssotski: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index dce2eaf..824a87d 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -76,7 +76,14 @@
/* * This controls the device -> IRQ routing. - * The PIC values are limited to 0,1, 3 - 12, 14, 15. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 <- ec/google/chromeec/acpi/superio.asl + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + * 12: i8042 <- ec/google/chromeec/acpi/superio.asl */ static const struct fch_irq_routing { uint8_t intr_index; @@ -84,9 +91,14 @@ uint8_t apic_irq_num; } fch_pirq[] = { { PIRQ_A, 6, 16 }, - { PIRQ_B, 6, 17 }, + { PIRQ_B, 13, 17 }, { PIRQ_C, 14, 18 }, { PIRQ_D, 15, 19 }, + { PIRQ_E, 15, 20 }, + { PIRQ_F, 14, 21 }, + { PIRQ_G, 13, 22 }, + { PIRQ_H, 6, 23 }, + { PIRQ_SCI, 9, 9 }, { PIRQ_EMMC, 5, 5 }, { PIRQ_GPIO, 7, 7 },
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Felix Held (Code Review) -
Nikolai Vyssotski (Code Review)
-
Raul Rangel (Code Review)