Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
soc/intel/common/block/acpi: Factor out common gfx.asl
This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f --- M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/gfx.asl 2 files changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45997/1
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 0c092e1..35dc196 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif
/* GFX 00:02.0 */ -#include "gfx.asl" +#include <soc/intel/common/block/acpi/acpi/gfx.asl>
/* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/common/block/acpi/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/soc/intel/common/block/acpi/acpi/gfx.asl
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/block/acpi: Factor out common gfx.asl Hrm, I only see this on one SoC. Do other SoCs not describe the iGPU in ACPI?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/block/acpi: Factor out common gfx.asl
Hrm, I only see this on one SoC. […]
Yes Angel, this is very weird in my opinion, ideally it need to have IGD entry as well. we can park this CL till the time, i would get more details from Chrome OS team.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/block/acpi: Factor out common gfx.asl
Yes Angel, this is very weird in my opinion, ideally it need to have IGD entry as well. […]
Looks like it was added in CB:36043
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/block/acpi: Factor out common gfx.asl
Looks like it was added in CB:36043
Thanks Angel, i will talk to Duncan and possible this code is required for other SOC as well as it looks must have for drallion
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
Hi Duncan,
Do you think we need to add IGD ASL device entry for other SOC as well?
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1: Code-Review+2
Patch Set 1:
Hi Duncan,
Do you think we need to add IGD ASL device entry for other SOC as well?
It is probably good to be consistent and add it in the common code for other SOC. The entry itself in the DSDT doesn't do much but it allows the ports to be defined in devicetree and get generated in the SSDT.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+2
Patch Set 1:
Hi Duncan,
Do you think we need to add IGD ASL device entry for other SOC as well?
It is probably good to be consistent and add it in the common code for other SOC. The entry itself in the DSDT doesn't do much but it allows the ports to be defined in devicetree and get generated in the SSDT.
Thanks Duncan, i will add gfx.asl for other SoC as well to ensure its align.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1: Code-Review+2
Patch Set 1:
Patch Set 1: Code-Review+2
Patch Set 1:
Hi Duncan,
Do you think we need to add IGD ASL device entry for other SOC as well?
It is probably good to be consistent and add it in the common code for other SOC. The entry itself in the DSDT doesn't do much but it allows the ports to be defined in devicetree and get generated in the SSDT.
Thanks Duncan, i will add gfx.asl for other SoC as well to ensure its align.
Thanks for the clarification.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45997/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/common/block/acpi: Factor out common gfx.asl
Thanks Angel, i will talk to Duncan and possible this code is required for other SOC as well as it l […]
Ack
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45997 )
Change subject: soc/intel/common/block/acpi: Factor out common gfx.asl ......................................................................
soc/intel/common/block/acpi: Factor out common gfx.asl
This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/gfx.asl 2 files changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 0c092e1..35dc196 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif
/* GFX 00:02.0 */ -#include "gfx.asl" +#include <soc/intel/common/block/acpi/acpi/gfx.asl>
/* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/acpi/gfx.asl b/src/soc/intel/common/block/acpi/acpi/gfx.asl similarity index 100% rename from src/soc/intel/cannonlake/acpi/gfx.asl rename to src/soc/intel/common/block/acpi/acpi/gfx.asl
-
Angel Pons (Code Review) -
Duncan Laurie (Code Review)
-
Subrata Banik (Code Review)