Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23041
Change subject: [WIP]sandybridge/optimus: Incomplete Optimus port ......................................................................
[WIP]sandybridge/optimus: Incomplete Optimus port
Change-Id: If1d46e063d1856db2fe7d71bc2219e3aded1f935 Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/mainboard/lenovo/t530/dsdt.asl M src/northbridge/intel/sandybridge/acpi/peg.asl 2 files changed, 411 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/23041/1
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 7db8344..30a5119 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -49,6 +49,97 @@ #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } + + Scope (_SB.PCI0.PEGP.DEV0) { + Method (NVOP, 4, Serialized) { + If (LNotEqual (Arg1, 0x0100)) + { + Return (0x80000001) + } + + Store (ToInteger (Arg2), Local0) + + /* Supported Optimus functions advertisement */ + If (LEqual (Local0, 0x00)) + { + Return (Buffer (0x04) + { + 0x09, 0x00, 0x00, 0x06 + }) + } + /* NOUVEAU_DSM_OPTIMUS_CAPS */ + If (LEqual (Local0, 0x1A)) + { + CreateField (Arg3, 0x18, 0x02, OPCE) + CreateField (Arg3, 0x00, 0x01, FLCH) + If (ToInteger (FLCH)) + { + Store (OPCE, OMPR) + } + + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x00, 0x01, OPEN) + CreateField (Local0, 0x03, 0x02, CGCS) + CreateField (Local0, 0x06, 0x01, SHPC) + CreateField (Local0, 0x18, 0x03, DGPC) + CreateField (Local0, 0x1B, 0x02, HDAC) + Store (One, OPEN) + Store (One, SHPC) + Store (One, DGPC) + If (_SB.PCI0.PEG.DEV0._STA ()) + { + Store (0x03, CGCS) + } + + Store (0x02, HDAC) + Return (Local0) + } + /* NOUVEAU_DSM_OPTIMUS_FLAGS */ + If (LEqual (Local0, 0x1B)) + { + CreateField (Arg3, 0x00, 0x01, HDAU) + CreateField (Arg3, 0x01, 0x01, HDAR) + Store (Buffer (0x04) + { + 0x00, 0x00, 0x00, 0x00 + }, Local0) + CreateField (Local0, 0x02, 0x02, RQGS) + CreateField (Local0, 0x04, 0x01, PWST) + Store (One, PWST) + Store (Zero, RQGS) + If (ToInteger (HDAR)) + { + Store (ToInteger (HDAU), HDAS) + } + + Return (Local0) + } + /* NOUVEAU_DSM_POWER */ + If (LEqual (Local0, 3)) + { + } + + Return (0x80000002) + } + + Method (_DSM, 4, NotSerialized) { + /* NV DSM OPTIMUS */ + If (\CMPB (Arg0, Buffer (0x10) { + 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, + 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0})) + { + Return (NVOP (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (0x04) + { + 0x01, 0x00, 0x00, 0x80 + }) + } + }
/* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index ddacdba..6b0f9ce 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -28,6 +28,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, _SB.PCI0.PEGP.LNKD) + Store(One, _SB.PCI0.PEGP.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(_SB.PCI0.PEGP.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, _SB.PCI0.PEGP.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + _SB.PCI0.PEGP._ON () + _SB.PCI0.PEGP.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + _SB.PCI0.PEGP.DEV0._OFF () + _SB.PCI0.PEGP._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) }
Device (PEG1) @@ -44,6 +124,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, _SB.PCI0.PEG1.LNKD) + Store(One, _SB.PCI0.PEG1.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(_SB.PCI0.PEG1.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, _SB.PCI0.PEG1.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + _SB.PCI0.PEG1._ON () + _SB.PCI0.PEG1.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + _SB.PCI0.PEG1.DEV0._OFF () + _SB.PCI0.PEG1._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) }
Device (PEG2) @@ -60,6 +220,86 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, _SB.PCI0.PEG2.LNKD) + Store(One, _SB.PCI0.PEG2.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(_SB.PCI0.PEG2.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, _SB.PCI0.PEG2.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + _SB.PCI0.PEG2._ON () + _SB.PCI0.PEG2.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + _SB.PCI0.PEG2.DEV0._OFF () + _SB.PCI0.PEG2._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) }
Device (PEG6) @@ -76,4 +316,84 @@ { Name(_ADR, 0x00000000) } + + OperationRegion (RPCS, PCI_Config, 0x00, 0x100) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + Offset (0xb0), // Link Capabilities + , 4, + LNKD, 1, // Link Disable + RTRL, 1, // Retrain Link + Offset (0xb2), // Link Status + , 10, + LNKT, 1, // Link Training + } + + Method (_ON) + { + Store(Zero, _SB.PCI0.PEG6.LNKD) + Store(One, _SB.PCI0.PEG6.RTRL) + + Store (0x32, Local1) + While (Local1) + { + Sleep (10) + If (LEqual(_SB.PCI0.PEG6.LNKT, 0)) + { + Break + } + + Decrement (Local1) + } + } + + Method (_OFF) + { + Store(One, _SB.PCI0.PEG6.LNKD) + } + + PowerResource (PWR1, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + _SB.PCI0.PEG6._ON () + _SB.PCI0.PEG6.DEV0._ON () + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + _SB.PCI0.PEG6.DEV0._OFF () + _SB.PCI0.PEG6._OFF () + Store (Zero, _STA) + } + } + + PowerResource (PWR2, 0x00, 0x0000) + { + Name (_STA, One) + Method (_ON, 0, Serialized) + { + Store (One, _STA) + } + + Method (_OFF, 0, Serialized) + { + Store (One, _STA) + } + } + + Name (_PR0, Package (0x01) + { + PWR1 + }) + Name (_PR2, Package (0x01) + { + PWR2 + }) + Name (_PR3, Package (0x01) + { + PWR1 + }) }
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Patrick Rudolph (Code Review)