[L] Change in coreboot[master]: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash

[Michał Żygowski (Code Review)]

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Paul Menzel, Krystian Hebel.

Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68987

to look at the new patch set (#5).

Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................

soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash

The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 functioning even if CSME/HECI is not functional.

TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.

Signed-off-by: Michał Żygowski 
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
---
M Makefile.inc
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/hsphy.c
M util/cbfstool/default-x86.fmd
5 files changed, 313 insertions(+), 42 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/5