Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage

[Felix Held (Code Review)]

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49929 )

Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage
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Patch Set 2:

(1 comment)

File src/soc/amd/cezanne/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/49929/comment/77a6354f_53020a26 
PS2, Line 16: #define I2C_MASTER_DEV_COUNT		4
            : #define I2C_MASTER_START_INDEX		2
            : #define I2C_SLAVE_DEV_COUNT		1
            : 
            : #define APU_I2C2_BASE			0xfedc4000
            : #define APU_I2C3_BASE			0xfedc5000
            : #define APU_I2C4_BASE			0xfedc6000
            : 
            : /* I2C parameters for lpc_read_resources */
            : #define I2C_BASE_ADDRESS		APU_I2C2_BASE
            : #define I2C_DEVICE_SIZE			0x00001000
            : #define I2C_DEVICE_COUNT		(I2C_MASTER_DEV_COUNT \
            : 	
the i2c defines seem to be unrelated